http://iis-projects.ee.ethz.ch/api.php?action=feedcontributions&user=Schaffner&feedformat=atomiis-projects - User contributions [en]2024-03-29T05:42:40ZUser contributionsMediaWiki 1.28.0http://iis-projects.ee.ethz.ch/index.php?title=Timing_Channel_Mitigations_for_RISC-V_Cores&diff=4559Timing Channel Mitigations for RISC-V Cores2019-02-01T10:32:35Z<p>Schaffner: </p>
<hr />
<div>==Introduction==<br />
<br />
[[File:Timing channels intel.png|thumb|800px|These two ''timing channel matrices'' of a Haswell class Intel processor show the conditional probability of observing an output symbol (vertical axis) given an input symbol (horizontal axis). The effect of timing mitigation techniques can be clearly observed in the right matrix, where almost no correlation can be observed anymore. Images taken from [http://ts.data61.csiro.au/projects/TS/timingchannels/arch-mitigation.pml].]]<br />
<br />
The Spectre and Meltdown vulnerabilities that publicly surfaced about a year ago did not only severely impact companies and cloud service providers, but also shook our trust in the computing systems we use on a daily basis, such as our laptops and mobile phones [masters2018]. These vulnerabilities are essentially a combination of speculative execution techniques present in today's processors, combined with shared hardware state and timing channels that make it possible to leak information. <br />
<br />
Timing channels are among the remaining unsolved problems in secure hardware architecture design, and it is argued that '''security needs a new hardware-software contract''' [Ge2018a], [Ge2018b]. Security is and has always been the operating system's (OS) job. For instance, memory protection is already well established - '''but the OS must also enforce time protection'''. In order to enforce time protection, additional hardware support for state flushing is required.<br />
<br />
In this project, we will investigate how such ''hardware knobs'' can be added to the Ariane 64bit RISC-V processor and come up with a proof-of-concept implementation. Insights gained during this process shall be fed back to the RISC-V community in order to guide the design of future secure RISC-V systems. <br />
<br />
==Project description==<br />
<br />
The purpose of this project is to enhance the Ariane RISC-V processor [arianeGit] with additional hardware mechanisms to flush the state of various functional and non-functional units in the pipeline. Specifically, we need to be able to erase state from <br />
<br />
* functional units,<br />
* instruction frontend,<br />
* translation look-aside buffer (TLBs),<br />
* branch predictor(s),<br />
* instruction and data caches<br />
<br />
in an effective way and with predictable or even constant latency [Ge2018a]. These ''knobs'' are then exposed to an OS that implements the mitigation techniques outlined in [Ge2018b].<br />
<br />
Your task will be to carry out and test the required hardware mechanisms both in simulation and on a FPGA mapping of the Ariane processor. Further, the power, area and timing impact of the implemented mechanisms shall be assessed by mapping the core to a modern ASIC technology. <br />
<br />
Depending on the project progress, initial experiments with the seL4 microkernel [seL4] can be carried out in collaboration with University of South Wales (UNSW).<br />
<br />
==Required Skills==<br />
To work on this project, you will need:<br />
* to have worked in the past with at least one RTL language (SystemVerilog or Verilog or VHDL) -- having followed the VLSI1 / VLSI2 courses is mandatory<br />
* to have prior knowledge of hardware design and computer architecture -- having followed the "Advanced System-on-Chip Design" or "Energy-Efficient Parallel Computing Systems for Data Analytics" course is recommended<br />
<br />
Other skills that you might find useful include:<br />
* familiarity with git, the UNIX shell, C programming<br />
* familiarity with basic system security principles<br />
<br />
===Status: Available===<br />
: Looking for a Semester Thesis student<br />
: Supervision: [[:User:Schaffner|Michael Schaffner]], [[:User:Zarubaf|Florian Zaruba]], [[:User:Scmoritz|Moritz Schneider]]<br />
<br />
===Professors===<br />
: [https://www.ee.ethz.ch/the-department/people-a-z/person-detail.html?persid=194234 Luca Benini, ETH Zurich]<br />
: [http://ts.data61.csiro.au/people/?cn=Gernot+Heiser Gernot Heiser, UNSW, Sydney]<br />
<br />
==Practical Details==<br />
<br />
===Meetings & Presentations===<br />
The students and advisor(s) agree on weekly meetings to discuss all relevant decisions and decide on how to proceed. Of course, additional meetings can be organized to address urgent issues. <br />
<br />
At the end of the project, you have to present/defend your work during a 15 min. presentation and 5 min. of discussion as part of the IIS colloquium.<br />
<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Resources==<br />
* [masters2018] Jon Masters, Red Hat Inc. "Exploiting modern microarchitectures: Meltdown, Spectre, and other attacks" [https://people.redhat.com/jcm/talks/FOSDEM_2018.pdf]<br />
* [arianeGit] Ariane is a 6-stage, single issue, in-order CPU which implements the 64-bit RISC-V instruction set [https://github.com/pulp-platform/ariane]<br />
* [Zaruba2018] Zaruba, Florian "Ariane: An open-source 64-bit RISC-V Application-Class Processor and latest Improvements" [https://content.riscv.org/wp-content/uploads/2018/05/14.15-14.40-FlorianZaruba_riscv_workshop-1.pdf]<br />
* [data61timing] Gernot Heiser, et al. "Mitigating microarchitectural timing channels with hardware-provided operations" [http://ts.data61.csiro.au/projects/TS/timingchannels/arch-mitigation.pml]<br />
* [Ge2018a] Ge, Qian et al. "No Security Without Time Protection: We Need a New Hardware-Software Contract." [https://ts.data61.csiro.au/publications/csiro_full_text//Ge_YH_18.pdf]<br />
* [Ge2018b] Ge, Qian et al. "Time Protection: the Missing OS Abstraction." [https://ts.data61.csiro.au/publications/papers/Ge_YCH_18_1.pdf]<br />
* [seL4] The seL4 microkernel [https://ts.data61.csiro.au/projects/seL4/]<br />
<br />
==Links== <br />
* The EDA wiki with lots of information on the ETHZ ASIC design flow (internal only) [http://eda.ee.ethz.ch/]<br />
* The IIS/DZ coding guidelines [http://eda.ee.ethz.ch/index.php/Naming_Conventions]<br />
<br />
[[Category:Processor]]<br />
[[Category:Computer Architecture]]<br />
[[Category:Digital]] <br />
[[Category:Security]]<br />
[[Category:PULP]]<br />
[[Category:FPGA]] <br />
[[Category:ASIC]] <br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
<br />
<!-- <br />
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[[Category:Nano Electronics]]<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Hot]]<br />
<br />
TYPE OF WORK<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
[[Category:Research]]<br />
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NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:UltrasoundToGo]]<br />
[[Category:IcySoC]]<br />
[[Category:PSocrates]]<br />
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[[Category:2010]]<br />
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[[Category:2013]]<br />
[[Category:2014]]<br />
<br />
---></div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=Timing_Channel_Mitigations_for_RISC-V_Cores&diff=4558Timing Channel Mitigations for RISC-V Cores2019-02-01T10:32:20Z<p>Schaffner: </p>
<hr />
<div>==Introduction==<br />
<br />
[[File:Timing channels intel.png|thumb|800px|These two ''timing channel matrices'' of a Haswell class Intel processor show the conditional probability of observing an output symbol (vertical axis) given an input symbol (horizontal axis). The effect of timing mitigation techniques can be clearly observed in the right matrix, where almost no correlation can be observed anymore. Images taken from [http://ts.data61.csiro.au/projects/TS/timingchannels/arch-mitigation.pml].]]<br />
<br />
The Spectre and Meltdown vulnerabilities that publicly surfaced about a year ago did not only severely impact companies and cloud service providers, but also shook our trust in the computing systems we use on a daily basis, such as our laptops and mobile phones [masters2018]. These vulnerabilities are essentially a combination of speculative execution techniques present in today's processors, combined with shared hardware state and timing channels that make it possible to leak information. <br />
<br />
Timing channels are among the remaining unsolved problems in secure hardware architecture design, and it is argued that '''security needs a new hardware-software contract''' [Ge2018a], [Ge2018b]. Security is and has always been the operating system's (OS) job. For instance, memory protection is already well established - '''but the OS must also enforce time protection'''. In order to enforce time protection, additional hardware support for state flushing is required.<br />
<br />
In this project, we will investigate how such ''hardware knobs'' can be added to the Ariane 64bit RISC-V processor and come up with a proof-of-concept implementation. Insights gained during this process shall be fed back to the RISC-V community in order to guide the design of future secure RISC-V systems. <br />
<br />
==Project description==<br />
<br />
The purpose of this project is to enhance the Ariane RISC-V processor [arianeGit] with additional hardware mechanisms to flush the state of various functional and non-functional units in the pipeline. Specifically, we need to be able to erase state from <br />
<br />
* functional units,<br />
* instruction frontend,<br />
* translation look-aside buffer (TLBs),<br />
* branch predictor(s),<br />
* instruction and data caches<br />
<br />
in an effective way and with predictable or even constant latency [Ge2018a]. These ''knobs'' are then exposed to an OS that implements the mitigation techniques outlined in [Ge2018b].<br />
<br />
Your task will be to carry out and test the required hardware mechanisms both in simulation and on a FPGA mapping of the Ariane processor. Further, the power, area and timing impact of the implemented mechanisms shall be assessed by mapping the core to a modern ASIC technology. Depending on the project progress, initial experiments with the seL4 microkernel [seL4] can be carried out in collaboration with University of South Wales (UNSW).<br />
<br />
==Required Skills==<br />
To work on this project, you will need:<br />
* to have worked in the past with at least one RTL language (SystemVerilog or Verilog or VHDL) -- having followed the VLSI1 / VLSI2 courses is mandatory<br />
* to have prior knowledge of hardware design and computer architecture -- having followed the "Advanced System-on-Chip Design" or "Energy-Efficient Parallel Computing Systems for Data Analytics" course is recommended<br />
<br />
Other skills that you might find useful include:<br />
* familiarity with git, the UNIX shell, C programming<br />
* familiarity with basic system security principles<br />
<br />
===Status: Available===<br />
: Looking for a Semester Thesis student<br />
: Supervision: [[:User:Schaffner|Michael Schaffner]], [[:User:Zarubaf|Florian Zaruba]], [[:User:Scmoritz|Moritz Schneider]]<br />
<br />
===Professors===<br />
: [https://www.ee.ethz.ch/the-department/people-a-z/person-detail.html?persid=194234 Luca Benini, ETH Zurich]<br />
: [http://ts.data61.csiro.au/people/?cn=Gernot+Heiser Gernot Heiser, UNSW, Sydney]<br />
<br />
==Practical Details==<br />
<br />
===Meetings & Presentations===<br />
The students and advisor(s) agree on weekly meetings to discuss all relevant decisions and decide on how to proceed. Of course, additional meetings can be organized to address urgent issues. <br />
<br />
At the end of the project, you have to present/defend your work during a 15 min. presentation and 5 min. of discussion as part of the IIS colloquium.<br />
<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Resources==<br />
* [masters2018] Jon Masters, Red Hat Inc. "Exploiting modern microarchitectures: Meltdown, Spectre, and other attacks" [https://people.redhat.com/jcm/talks/FOSDEM_2018.pdf]<br />
* [arianeGit] Ariane is a 6-stage, single issue, in-order CPU which implements the 64-bit RISC-V instruction set [https://github.com/pulp-platform/ariane]<br />
* [Zaruba2018] Zaruba, Florian "Ariane: An open-source 64-bit RISC-V Application-Class Processor and latest Improvements" [https://content.riscv.org/wp-content/uploads/2018/05/14.15-14.40-FlorianZaruba_riscv_workshop-1.pdf]<br />
* [data61timing] Gernot Heiser, et al. "Mitigating microarchitectural timing channels with hardware-provided operations" [http://ts.data61.csiro.au/projects/TS/timingchannels/arch-mitigation.pml]<br />
* [Ge2018a] Ge, Qian et al. "No Security Without Time Protection: We Need a New Hardware-Software Contract." [https://ts.data61.csiro.au/publications/csiro_full_text//Ge_YH_18.pdf]<br />
* [Ge2018b] Ge, Qian et al. "Time Protection: the Missing OS Abstraction." [https://ts.data61.csiro.au/publications/papers/Ge_YCH_18_1.pdf]<br />
* [seL4] The seL4 microkernel [https://ts.data61.csiro.au/projects/seL4/]<br />
<br />
==Links== <br />
* The EDA wiki with lots of information on the ETHZ ASIC design flow (internal only) [http://eda.ee.ethz.ch/]<br />
* The IIS/DZ coding guidelines [http://eda.ee.ethz.ch/index.php/Naming_Conventions]<br />
<br />
[[Category:Processor]]<br />
[[Category:Computer Architecture]]<br />
[[Category:Digital]] <br />
[[Category:Security]]<br />
[[Category:PULP]]<br />
[[Category:FPGA]] <br />
[[Category:ASIC]] <br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
[[Category:Digital]]<br />
[[Category:Analog]]<br />
[[Category:Nano-TCAD]]<br />
[[Category:Nano Electronics]]<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Hot]]<br />
<br />
TYPE OF WORK<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
[[Category:Research]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:UltrasoundToGo]]<br />
[[Category:IcySoC]]<br />
[[Category:PSocrates]]<br />
[[Category:UlpSoC]]<br />
[[Category:Qcrypt]]<br />
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YEAR (IF FINISHED)<br />
[[Category:2010]]<br />
[[Category:2011]]<br />
[[Category:2012]]<br />
[[Category:2013]]<br />
[[Category:2014]]<br />
<br />
---></div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=Timing_Channel_Mitigations_for_RISC-V_Cores&diff=4557Timing Channel Mitigations for RISC-V Cores2019-02-01T10:31:48Z<p>Schaffner: </p>
<hr />
<div>==Introduction==<br />
<br />
[[File:Timing channels intel.png|thumb|800px|These two ''timing channel matrices'' of a Haswell class Intel processor show the conditional probability of observing an output symbol (vertical axis) given an input symbol (horizontal axis). The effect of timing mitigation techniques can be clearly observed in the right matrix, where almost no correlation can be observed anymore. Images taken from [http://ts.data61.csiro.au/projects/TS/timingchannels/arch-mitigation.pml].]]<br />
<br />
The Spectre and Meltdown vulnerabilities that publicly surfaced about a year ago did not only severely impact companies and cloud service providers, but also shook our trust in the computing systems we use on a daily basis, such as our laptops and mobile phones [masters2018]. These vulnerabilities are essentially a combination of speculative execution techniques present in today's processors, combined with shared hardware state and timing channels that make it possible to leak information. <br />
<br />
Timing channels are among the remaining unsolved problems in secure hardware architecture design, and it is argued that '''security needs a new hardware-software contract''' [Ge2018a], [Ge2018b]. Security is and has always been the operating system's (OS) job. For instance, memory protection is already well established - '''but the OS must also enforce time protection'''. In order to enforce time protection, additional hardware support for state flushing is required.<br />
<br />
In this project, we will investigate how such ''hardware knobs'' can be added to the Ariane 64bit RISC-V processor and come up with a proof-of-concept implementation. Insights gained during this process shall be fed back to the RISC-V community in order to guide the design of future secure RISC-V systems. <br />
<br />
==Project description==<br />
<br />
The purpose of this project is to enhance the Ariane RISC-V processor [arianeGit] with additional hardware mechanisms to flush the state of various functional and non-functional units in the pipeline. Specifically, we need to be able to erase state from <br />
<br />
* functional units,<br />
* instruction frontend,<br />
* translation look-aside buffer (TLBs),<br />
* branch predictor(s),<br />
* instruction and data caches<br />
<br />
in an effective way and with predictable or even constant latency [Ge2018a]. These ''knobs'' are then exposed to an OS that implements the mitigation techniques outlined in [Ge2018b].<br />
<br />
Your task will be to carry out and test the required hardware mechanisms both in simulation and on a FPGA mapping of the Ariane processor. Further, the power, area and timing impact of the implemented mechanisms shall be assessed by mapping the core to a modern ASIC technology. Depending on the project progress, initial experiments with the seL4 microkernel [seL4] can be carried out in collaboration with University of South Wales (UNSW).<br />
<br />
==Required Skills==<br />
To work on this project, you will need:<br />
* to have worked in the past with at least one RTL language (SystemVerilog or Verilog or VHDL) -- having followed the VLSI1 / VLSI2 courses is mandatory<br />
* to have prior knowledge of hardware design and computer architecture -- having followed the "Advanced System-on-Chip Design" or "Energy-Efficient Parallel Computing Systems for Data Analytics" course is recommended<br />
<br />
Other skills that you might find useful include:<br />
* familiarity with git, the UNIX shell, C programming<br />
* familiarity with basic system security principles<br />
<br />
===Status: Available===<br />
: Looking for a Semester Thesis student<br />
: Supervision: [[:User:Schaffner|Michael Schaffner]], [[:User:Zarubaf|Florian Zaruba]], [[:User:Scmoritz|Moritz Schneider]]<br />
<br />
===Professors===<br />
: [https://www.ee.ethz.ch/the-department/people-a-z/person-detail.html?persid=194234 Luca Benini, ETH Zurich]<br />
: [http://ts.data61.csiro.au/people/?cn=Gernot+Heiser Gernot Heiser, UNSW, Sydney]<br />
<br />
==Practical Details==<br />
<br />
===Meetings & Presentations===<br />
The students and advisor(s) agree on weekly meetings to discuss all relevant decisions and decide on how to proceed. Of course, additional meetings can be organized to address urgent issues. <br />
<br />
At the end of the project, you have to present/defend your work during a 15 min. presentation and 5 min. of discussion as part of the IIS colloquium.<br />
<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Resources==<br />
* [masters2018] Jon Masters, Red Hat Inc. "Exploiting modern microarchitectures: Meltdown, Spectre, and other attacks" [https://people.redhat.com/jcm/talks/FOSDEM_2018.pdf]<br />
* [arianeGit] Ariane is a 6-stage, single issue, in-order CPU which implements the 64-bit RISC-V instruction set [https://github.com/pulp-platform/ariane]<br />
* [Zaruba2018] Zaruba, Florian "Ariane: An open-source 64-bit RISC-V Application-Class Processor and latest Improvements" [https://content.riscv.org/wp-content/uploads/2018/05/14.15-14.40-FlorianZaruba_riscv_workshop-1.pdf]<br />
* [data61timing] Gernot Heiser, et al. "Mitigating microarchitectural timing channels with hardware-provided operations" [http://ts.data61.csiro.au/projects/TS/timingchannels/arch-mitigation.pml]<br />
* [Ge2018a] Ge, Qian et al. "No Security Without Time Protection: We Need a New Hardware-Software Contract." [https://ts.data61.csiro.au/publications/csiro_full_text//Ge_YH_18.pdf]<br />
* [Ge2018b] Ge, Qian et al. "Time Protection: the Missing OS Abstraction." [https://ts.data61.csiro.au/publications/papers/Ge_YCH_18_1.pdf]<br />
* [seL4] The seL4 microkernel [https://ts.data61.csiro.au/projects/seL4/]<br />
<br />
==Links== <br />
* The EDA wiki with lots of information on the ETHZ ASIC design flow (internal only) [http://eda.ee.ethz.ch/]<br />
* The IIS/DZ coding guidelines [http://eda.ee.ethz.ch/index.php/Naming_Conventions]<br />
<br />
[[Category:Processor]]<br />
[[Category:Computer Architecture]]<br />
[[Category:Digital]] <br />
[[Category:Security]]<br />
[[Category:PULP]]<br />
[[Category:FPGA]] <br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
[[Category:Digital]]<br />
[[Category:Analog]]<br />
[[Category:Nano-TCAD]]<br />
[[Category:Nano Electronics]]<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Hot]]<br />
<br />
TYPE OF WORK<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
[[Category:Research]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:UltrasoundToGo]]<br />
[[Category:IcySoC]]<br />
[[Category:PSocrates]]<br />
[[Category:UlpSoC]]<br />
[[Category:Qcrypt]]<br />
<br />
YEAR (IF FINISHED)<br />
[[Category:2010]]<br />
[[Category:2011]]<br />
[[Category:2012]]<br />
[[Category:2013]]<br />
[[Category:2014]]<br />
<br />
---></div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=Timing_Channel_Mitigations_for_RISC-V_Cores&diff=4552Timing Channel Mitigations for RISC-V Cores2019-01-31T11:30:38Z<p>Schaffner: </p>
<hr />
<div>==Introduction==<br />
<br />
[[File:Timing channels intel.png|thumb|800px|These two ''timing channel matrices'' of a Haswell class Intel processor show the conditional probability of observing an output symbol (vertical axis) given an input symbol (horizontal axis). The effect of timing mitigation techniques can be clearly observed in the right matrix, where almost no correlation can be observed anymore. Images taken from [http://ts.data61.csiro.au/projects/TS/timingchannels/arch-mitigation.pml].]]<br />
<br />
The Spectre and Meltdown vulnerabilities that publicly surfaced about a year ago did not only severely impact companies and cloud service providers, but also shook our trust in the computing systems we use on a daily basis, such as our laptops and mobile phones [masters2018]. These vulnerabilities are essentially a combination of speculative execution techniques present in today's processors, combined with shared hardware state and timing channels that make it possible to leak information. <br />
<br />
Timing channels are among the remaining unsolved problems in secure hardware architecture design, and it is argued that '''security needs a new hardware-software contract''' [Ge2018a], [Ge2018b]. Security is and has always been the operating system's (OS) job. For instance, memory protection is already well established - '''but the OS must also enforce time protection'''. In order to enforce time protection, additional hardware support for state flushing is required.<br />
<br />
In this project, we will investigate how such ''hardware knobs'' can be added to the Ariane 64bit RISC-V processor and come up with a proof-of-concept implementation. Insights gained during this process shall be fed back to the RISC-V community in order to guide the design of future secure RISC-V systems. <br />
<br />
==Project description==<br />
<br />
The purpose of this project is to enhance the Ariane RISC-V processor [arianeGit] with additional hardware mechanisms to flush the state of various functional and non-functional units in the pipeline. Specifically, we need to be able to erase state from <br />
<br />
* functional units,<br />
* translation look-aside buffer (TLBs),<br />
* branch predictor(s),<br />
* instruction and data caches<br />
<br />
in an effective way and with predictable or even constant latency [Ge2018a]. These ''knobs'' are then exposed to an OS that implements the mitigation techniques outlined in [Ge2019b].<br />
<br />
Your task will be to carry out and test the required hardware mechanisms both in simulation and on a FPGA mapping of the Ariane processor. Depending on the project progress, initial experiments with the seL4 microkernel [seL4] can be carried out in collaboration with University of South Wales (UNSW).<br />
<br />
==Required Skills==<br />
To work on this project, you will need:<br />
* to have worked in the past with at least one RTL language (SystemVerilog or Verilog or VHDL) -- having followed the VLSI1 / VLSI2 courses is recommended<br />
* to have prior knowledge of hardware design and computer architecture -- having followed the "Advanced System-on-Chip Design" or "Energy-Efficient Parallel Computing Systems for Data Analytics" course is recommended<br />
<br />
Other skills that you might find useful include:<br />
* familiarity with git, the UNIX shell, C programming<br />
* familiarity with basic system security principles<br />
<br />
===Status: Available===<br />
: Looking for a Semester Thesis student<br />
: Supervision: [[:User:Schaffner|Michael Schaffner]], [[:User:Zarubaf|Florian Zaruba]], [[:User:Scmoritz|Moritz Schneider]]<br />
<br />
===Professors===<br />
: [https://www.ee.ethz.ch/the-department/people-a-z/person-detail.html?persid=194234 Luca Benini, ETH Zurich]<br />
: [http://ts.data61.csiro.au/people/?cn=Gernot+Heiser Gernot Heiser, UNSW, Sydney]<br />
<br />
==Practical Details==<br />
<br />
===Meetings & Presentations===<br />
The students and advisor(s) agree on weekly meetings to discuss all relevant decisions and decide on how to proceed. Of course, additional meetings can be organized to address urgent issues. <br />
<br />
At the end of the project, you have to present/defend your work during a 15 min. presentation and 5 min. of discussion as part of the IIS colloquium.<br />
<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Resources==<br />
* [masters2018] Jon Masters, Red Hat Inc. "Exploiting modern microarchitectures: Meltdown, Spectre, and other attacks" [https://people.redhat.com/jcm/talks/FOSDEM_2018.pdf]<br />
* [arianeGit] Ariane is a 6-stage, single issue, in-order CPU which implements the 64-bit RISC-V instruction set [https://github.com/pulp-platform/ariane]<br />
* [Zaruba2018] Zaruba, Florian "Ariane: An open-source 64-bit RISC-V Application-Class Processor and latest Improvements" [https://content.riscv.org/wp-content/uploads/2018/05/14.15-14.40-FlorianZaruba_riscv_workshop-1.pdf]<br />
* [data61timing] Gernot Heiser, et al. "Mitigating microarchitectural timing channels with hardware-provided operations" [http://ts.data61.csiro.au/projects/TS/timingchannels/arch-mitigation.pml]<br />
* [Ge2018a] Ge, Qian et al. "No Security Without Time Protection: We Need a New Hardware-Software Contract." [https://ts.data61.csiro.au/publications/csiro_full_text//Ge_YH_18.pdf]<br />
* [Ge2018b] Ge, Qian et al. "Time Protection: the Missing OS Abstraction." [https://ts.data61.csiro.au/publications/papers/Ge_YCH_18_1.pdf]<br />
* [seL4] The seL4 microkernel [https://ts.data61.csiro.au/projects/seL4/]<br />
<br />
==Links== <br />
* The EDA wiki with lots of information on the ETHZ ASIC design flow (internal only) [http://eda.ee.ethz.ch/]<br />
* The IIS/DZ coding guidelines [http://eda.ee.ethz.ch/index.php/Naming_Conventions]<br />
<br />
[[Category:Processor]]<br />
[[Category:Computer Architecture]]<br />
[[Category:Digital]] <br />
[[Category:Security]]<br />
[[Category:PULP]]<br />
[[Category:FPGA]] <br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
[[Category:Digital]]<br />
[[Category:Analog]]<br />
[[Category:Nano-TCAD]]<br />
[[Category:Nano Electronics]]<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Hot]]<br />
<br />
TYPE OF WORK<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
[[Category:Research]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:UltrasoundToGo]]<br />
[[Category:IcySoC]]<br />
[[Category:PSocrates]]<br />
[[Category:UlpSoC]]<br />
[[Category:Qcrypt]]<br />
<br />
YEAR (IF FINISHED)<br />
[[Category:2010]]<br />
[[Category:2011]]<br />
[[Category:2012]]<br />
[[Category:2013]]<br />
[[Category:2014]]<br />
<br />
---></div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=Timing_Channel_Mitigations_for_RISC-V_Cores&diff=4551Timing Channel Mitigations for RISC-V Cores2019-01-31T11:23:29Z<p>Schaffner: </p>
<hr />
<div>==Introduction==<br />
<br />
[[File:Timing channels intel.png|thumb|800px|These two ''timing channel matrices'' of a Haswell class Intel processor show the conditional probability of observing an output symbol (vertical axis) given an input symbol (horizontal axis). The effect of timing mitigation techniques can be clearly observed in the right matrix, where almost no correlation can be observed anymore. Images taken from [http://ts.data61.csiro.au/projects/TS/timingchannels/arch-mitigation.pml].]]<br />
<br />
The Spectre and Meltdown vulnerabilities that publicly surfaced about a year ago did not only severely impact companies and cloud service providers, but also shook our trust in the computing systems we use on a daily basis, such as our laptops and mobile phones [masters2018]. These vulnerabilities are essentially a combination of speculative execution techniques present in today's processors, combined with shared hardware state and timing channels that make it possible to leak information. <br />
<br />
Timing channels are among the remaining unsolved problems in secure hardware architecture design, and it is argued that '''security needs a new hardware-software contract''' [Ge2018a], [Ge2018b]. Security is and has always been the operating system's (OS) job. For instance, memory protection is already well established - '''but the OS must also enforce time protection'''. In order to enforce time protection, additional hardware support for state flushing is required.<br />
<br />
In this project, we will investigate how such ''hardware knobs'' can be added to the Ariane 64bit RISC-V processor and come up with a proof-of-concept implementation. Insights gained during this process shall be fed back to the RISC-V community in order to guide the design of future secure RISC-V systems. <br />
<br />
==Project description==<br />
<br />
The purpose of this project is to enhance the Ariane RISC-V processor [arianeGit] with additional hardware mechanisms to flush the state of various functional and non-functional units in the pipeline. Specifically, we need to be able to erase state from <br />
<br />
* functional units,<br />
* translation look-aside buffer (TLBs),<br />
* branch predictor(s),<br />
* instruction and data caches<br />
<br />
in an effective way and with predictable or even constant latency [Ge2018a]. These ''knobs'' are then exposed to an OS that implements the mitigation techniques outlined in [Ge2019b].<br />
<br />
Your task will be to carry out and test the required hardware mechanisms both in simulation and on a FPGA mapping of the Ariane processor. Depending on the project progress, initial experiments with the seL4 microkernel [seL4] can be carried out in collaboration with University of South Wales (UNSW).<br />
<br />
==Required Skills==<br />
To work on this project, you will need:<br />
* to have worked in the past with at least one RTL language (SystemVerilog or Verilog or VHDL) -- having followed the VLSI1 / VLSI2 courses is recommended<br />
* to have prior knowledge of hardware design and computer architecture -- having followed the "Advanced System-on-Chip Design" or "Energy-Efficient Parallel Computing Systems for Data Analytics" course is recommended<br />
<br />
Other skills that you might find useful include:<br />
* familiarity with git, the UNIX shell, C programming<br />
* familiarity with basic system security principles<br />
<br />
===Status: Available===<br />
: Looking for a Semester Thesis student<br />
: Supervision: [[:User:Schaffner|Michael Schaffner]], [[:User:Zarubaf|Florian Zaruba]], [[:User:Scmoritz|Moritz Schneider]]<br />
<br />
===Professors===<br />
: [https://www.ee.ethz.ch/the-department/people-a-z/person-detail.html?persid=194234 Luca Benini, ETH Zurich]<br />
: [http://ts.data61.csiro.au/people/?cn=Gernot+Heiser Gernot Heiser, UNSW, Sydney]<br />
<br />
==Practical Details==<br />
<br />
===Meetings & Presentations===<br />
The students and advisor(s) agree on weekly meetings to discuss all relevant decisions and decide on how to proceed. Of course, additional meetings can be organized to address urgent issues. <br />
<br />
At the end of the project, you have to present/defend your work during a 15 min. presentation and 5 min. of discussion as part of the IIS colloquium.<br />
<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Resources==<br />
* [masters2018] Jon Masters, Red Hat Inc. "Exploiting modern microarchitectures: Meltdown, Spectre, and other attacks" [https://people.redhat.com/jcm/talks/FOSDEM_2018.pdf]<br />
* [arianeGit] Ariane is a 6-stage, single issue, in-order CPU which implements the 64-bit RISC-V instruction set [https://github.com/pulp-platform/ariane]<br />
* [Zaruba2018] Zaruba, Florian "Ariane: An open-source 64-bit RISC-V Application-Class Processor and latest Improvements" [https://content.riscv.org/wp-content/uploads/2018/05/14.15-14.40-FlorianZaruba_riscv_workshop-1.pdf]<br />
* [data61timing] Gernot Heiser, et al. "Mitigating microarchitectural timing channels with hardware-provided operations" [http://ts.data61.csiro.au/projects/TS/timingchannels/arch-mitigation.pml]<br />
* [Ge2018a] Ge, Qian et al. "No Security Without Time Protection: We Need a New Hardware-Software Contract." [https://ts.data61.csiro.au/publications/csiro_full_text//Ge_YH_18.pdf]<br />
* [Ge2018b] Ge, Qian et al. "Time Protection: the Missing OS Abstraction." [https://ts.data61.csiro.au/publications/papers/Ge_YCH_18_1.pdf]<br />
* [seL4] The seL4 microkernel [https://ts.data61.csiro.au/projects/seL4/]<br />
<br />
==Links== <br />
* The EDA wiki with lots of information on the ETHZ ASIC design flow (internal only) [http://eda.ee.ethz.ch/]<br />
* The IIS/DZ coding guidelines [http://eda.ee.ethz.ch/index.php/Naming_Conventions]<br />
<br />
[[Category:Processor]]<br />
[[Category:Computer Architecture]]<br />
[[Category:Digital]] <br />
[[Category:Security]]<br />
[[Category:PULP]]<br />
[[Category:FPGA]] <br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:HOT]] <br />
<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
[[Category:Digital]]<br />
[[Category:Analog]]<br />
[[Category:Nano-TCAD]]<br />
[[Category:Nano Electronics]]<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Hot]]<br />
<br />
TYPE OF WORK<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
[[Category:Research]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:UltrasoundToGo]]<br />
[[Category:IcySoC]]<br />
[[Category:PSocrates]]<br />
[[Category:UlpSoC]]<br />
[[Category:Qcrypt]]<br />
<br />
YEAR (IF FINISHED)<br />
[[Category:2010]]<br />
[[Category:2011]]<br />
[[Category:2012]]<br />
[[Category:2013]]<br />
[[Category:2014]]<br />
<br />
---></div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=Timing_Channel_Mitigations_for_RISC-V_Cores&diff=4550Timing Channel Mitigations for RISC-V Cores2019-01-31T11:23:10Z<p>Schaffner: </p>
<hr />
<div>==Introduction==<br />
<br />
[[File:Timing channels intel.png|thumb|800px|These two ''timing channel matrices'' of a Haswell class Intel processor show the conditional probability of observing an output symbol (vertical axis) given an input symbol (horizontal axis). The effect of timing mitigation techniques can be clearly observed in the right matrix, where almost no correlation can be observed anymore. Images taken from [http://ts.data61.csiro.au/projects/TS/timingchannels/arch-mitigation.pml].]]<br />
<br />
The Spectre and Meltdown vulnerabilities that publicly surfaced about a year ago did not only severely impact companies and cloud service providers, but also shook our trust in the computing systems we use on a daily basis, such as our laptops and mobile phones [masters2018]. These vulnerabilities are essentially a combination of speculative execution techniques present in today's processors, combined with shared hardware state and timing channels that make it possible to leak information. <br />
<br />
Timing channels are among the remaining unsolved problems in secure hardware architecture design, and it is argued that '''security needs a new hardware-software contract''' [Ge2018a], [Ge2018b]. Security is and has always been the operating system's (OS) job. For instance, memory protection is already well established - but the OS must also enforce time protection. In order to enforce time protection, additional hardware support for state flushing is required.<br />
<br />
In this project, we will investigate how such ''hardware knobs'' can be added to the Ariane 64bit RISC-V processor and come up with a proof-of-concept implementation. Insights gained during this process shall be fed back to the RISC-V community in order to guide the design of future secure RISC-V systems. <br />
<br />
==Project description==<br />
<br />
The purpose of this project is to enhance the Ariane RISC-V processor [arianeGit] with additional hardware mechanisms to flush the state of various functional and non-functional units in the pipeline. Specifically, we need to be able to erase state from <br />
<br />
* functional units,<br />
* translation look-aside buffer (TLBs),<br />
* branch predictor(s),<br />
* instruction and data caches<br />
<br />
in an effective way and with predictable or even constant latency [Ge2018a]. These ''knobs'' are then exposed to an OS that implements the mitigation techniques outlined in [Ge2019b].<br />
<br />
Your task will be to carry out and test the required hardware mechanisms both in simulation and on a FPGA mapping of the Ariane processor. Depending on the project progress, initial experiments with the seL4 microkernel [seL4] can be carried out in collaboration with University of South Wales (UNSW).<br />
<br />
==Required Skills==<br />
To work on this project, you will need:<br />
* to have worked in the past with at least one RTL language (SystemVerilog or Verilog or VHDL) -- having followed the VLSI1 / VLSI2 courses is recommended<br />
* to have prior knowledge of hardware design and computer architecture -- having followed the "Advanced System-on-Chip Design" or "Energy-Efficient Parallel Computing Systems for Data Analytics" course is recommended<br />
<br />
Other skills that you might find useful include:<br />
* familiarity with git, the UNIX shell, C programming<br />
* familiarity with basic system security principles<br />
<br />
===Status: Available===<br />
: Looking for a Semester Thesis student<br />
: Supervision: [[:User:Schaffner|Michael Schaffner]], [[:User:Zarubaf|Florian Zaruba]], [[:User:Scmoritz|Moritz Schneider]]<br />
<br />
===Professors===<br />
: [https://www.ee.ethz.ch/the-department/people-a-z/person-detail.html?persid=194234 Luca Benini, ETH Zurich]<br />
: [http://ts.data61.csiro.au/people/?cn=Gernot+Heiser Gernot Heiser, UNSW, Sydney]<br />
<br />
==Practical Details==<br />
<br />
===Meetings & Presentations===<br />
The students and advisor(s) agree on weekly meetings to discuss all relevant decisions and decide on how to proceed. Of course, additional meetings can be organized to address urgent issues. <br />
<br />
At the end of the project, you have to present/defend your work during a 15 min. presentation and 5 min. of discussion as part of the IIS colloquium.<br />
<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Resources==<br />
* [masters2018] Jon Masters, Red Hat Inc. "Exploiting modern microarchitectures: Meltdown, Spectre, and other attacks" [https://people.redhat.com/jcm/talks/FOSDEM_2018.pdf]<br />
* [arianeGit] Ariane is a 6-stage, single issue, in-order CPU which implements the 64-bit RISC-V instruction set [https://github.com/pulp-platform/ariane]<br />
* [Zaruba2018] Zaruba, Florian "Ariane: An open-source 64-bit RISC-V Application-Class Processor and latest Improvements" [https://content.riscv.org/wp-content/uploads/2018/05/14.15-14.40-FlorianZaruba_riscv_workshop-1.pdf]<br />
* [data61timing] Gernot Heiser, et al. "Mitigating microarchitectural timing channels with hardware-provided operations" [http://ts.data61.csiro.au/projects/TS/timingchannels/arch-mitigation.pml]<br />
* [Ge2018a] Ge, Qian et al. "No Security Without Time Protection: We Need a New Hardware-Software Contract." [https://ts.data61.csiro.au/publications/csiro_full_text//Ge_YH_18.pdf]<br />
* [Ge2018b] Ge, Qian et al. "Time Protection: the Missing OS Abstraction." [https://ts.data61.csiro.au/publications/papers/Ge_YCH_18_1.pdf]<br />
* [seL4] The seL4 microkernel [https://ts.data61.csiro.au/projects/seL4/]<br />
<br />
==Links== <br />
* The EDA wiki with lots of information on the ETHZ ASIC design flow (internal only) [http://eda.ee.ethz.ch/]<br />
* The IIS/DZ coding guidelines [http://eda.ee.ethz.ch/index.php/Naming_Conventions]<br />
<br />
[[Category:Processor]]<br />
[[Category:Computer Architecture]]<br />
[[Category:Digital]] <br />
[[Category:Security]]<br />
[[Category:PULP]]<br />
[[Category:FPGA]] <br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:HOT]] <br />
<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
[[Category:Digital]]<br />
[[Category:Analog]]<br />
[[Category:Nano-TCAD]]<br />
[[Category:Nano Electronics]]<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Hot]]<br />
<br />
TYPE OF WORK<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
[[Category:Research]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:UltrasoundToGo]]<br />
[[Category:IcySoC]]<br />
[[Category:PSocrates]]<br />
[[Category:UlpSoC]]<br />
[[Category:Qcrypt]]<br />
<br />
YEAR (IF FINISHED)<br />
[[Category:2010]]<br />
[[Category:2011]]<br />
[[Category:2012]]<br />
[[Category:2013]]<br />
[[Category:2014]]<br />
<br />
---></div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=Timing_Channel_Mitigations_for_RISC-V_Cores&diff=4549Timing Channel Mitigations for RISC-V Cores2019-01-31T11:22:22Z<p>Schaffner: </p>
<hr />
<div>==Introduction==<br />
<br />
[[File:Timing channels intel.png|thumb|800px|These two ''timing channel matrices'' of a Haswell class Intel processor show the conditional probability of observing an output symbol (vertical axis) given an input symbol (horizontal axis). The effect of timing mitigation techniques can be clearly observed in the right matrix, where almost no correlation can be observed anymore. Images taken from [http://ts.data61.csiro.au/projects/TS/timingchannels/arch-mitigation.pml].]]<br />
<br />
The Spectre and Meltdown vulnerabilities that publicly surfaced about a year ago did not only severely impact companies and cloud service providers, but also shook our trust in the computing systems we use on a daily basis, such as our laptops and mobile phones [masters2018]. These vulnerabilities are essentially a combination of speculative execution techniques present in today's processors, combined with shared hardware state and timing channels that make it possible to leak information via covert channels. <br />
<br />
Such timing channels are among the remaining unsolved problems in secure hardware architecture design, and it is argued that '''security needs a new hardware-software contract''' [Ge2018a], [Ge2018b]. Security is and has always been the operating system's (OS) job. For instance, memory protection is already well established - but the OS must also enforce time protection. In order to enforce time protection, additional hardware support for state flushing is required.<br />
<br />
In this project, we will investigate how such ''hardware knobs'' can be added to the Ariane 64bit RISC-V processor and come up with a proof-of-concept implementation. Insights gained during this process shall be fed back to the RISC-V community in order to guide the design of future secure RISC-V systems. <br />
<br />
==Project description==<br />
<br />
The purpose of this project is to enhance the Ariane RISC-V processor [arianeGit] with additional hardware mechanisms to flush the state of various functional and non-functional units in the pipeline. Specifically, we need to be able to erase state from <br />
<br />
* functional units,<br />
* translation look-aside buffer (TLBs),<br />
* branch predictor(s),<br />
* instruction and data caches<br />
<br />
in an effective way and with predictable or even constant latency [Ge2018a]. These ''knobs'' are then exposed to an OS that implements the mitigation techniques outlined in [Ge2019b].<br />
<br />
Your task will be to carry out and test the required hardware mechanisms both in simulation and on a FPGA mapping of the Ariane processor. Depending on the project progress, initial experiments with the seL4 microkernel [seL4] can be carried out in collaboration with University of South Wales (UNSW).<br />
<br />
==Required Skills==<br />
To work on this project, you will need:<br />
* to have worked in the past with at least one RTL language (SystemVerilog or Verilog or VHDL) -- having followed the VLSI1 / VLSI2 courses is recommended<br />
* to have prior knowledge of hardware design and computer architecture -- having followed the "Advanced System-on-Chip Design" or "Energy-Efficient Parallel Computing Systems for Data Analytics" course is recommended<br />
<br />
Other skills that you might find useful include:<br />
* familiarity with git, the UNIX shell, C programming<br />
* familiarity with basic system security principles<br />
<br />
===Status: Available===<br />
: Looking for a Semester Thesis student<br />
: Supervision: [[:User:Schaffner|Michael Schaffner]], [[:User:Zarubaf|Florian Zaruba]], [[:User:Scmoritz|Moritz Schneider]]<br />
<br />
===Professors===<br />
: [https://www.ee.ethz.ch/the-department/people-a-z/person-detail.html?persid=194234 Luca Benini, ETH Zurich]<br />
: [http://ts.data61.csiro.au/people/?cn=Gernot+Heiser Gernot Heiser, UNSW, Sydney]<br />
<br />
==Practical Details==<br />
<br />
===Meetings & Presentations===<br />
The students and advisor(s) agree on weekly meetings to discuss all relevant decisions and decide on how to proceed. Of course, additional meetings can be organized to address urgent issues. <br />
<br />
At the end of the project, you have to present/defend your work during a 15 min. presentation and 5 min. of discussion as part of the IIS colloquium.<br />
<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Resources==<br />
* [masters2018] Jon Masters, Red Hat Inc. "Exploiting modern microarchitectures: Meltdown, Spectre, and other attacks" [https://people.redhat.com/jcm/talks/FOSDEM_2018.pdf]<br />
* [arianeGit] Ariane is a 6-stage, single issue, in-order CPU which implements the 64-bit RISC-V instruction set [https://github.com/pulp-platform/ariane]<br />
* [Zaruba2018] Zaruba, Florian "Ariane: An open-source 64-bit RISC-V Application-Class Processor and latest Improvements" [https://content.riscv.org/wp-content/uploads/2018/05/14.15-14.40-FlorianZaruba_riscv_workshop-1.pdf]<br />
* [data61timing] Gernot Heiser, et al. "Mitigating microarchitectural timing channels with hardware-provided operations" [http://ts.data61.csiro.au/projects/TS/timingchannels/arch-mitigation.pml]<br />
* [Ge2018a] Ge, Qian et al. "No Security Without Time Protection: We Need a New Hardware-Software Contract." [https://ts.data61.csiro.au/publications/csiro_full_text//Ge_YH_18.pdf]<br />
* [Ge2018b] Ge, Qian et al. "Time Protection: the Missing OS Abstraction." [https://ts.data61.csiro.au/publications/papers/Ge_YCH_18_1.pdf]<br />
* [seL4] The seL4 microkernel [https://ts.data61.csiro.au/projects/seL4/]<br />
<br />
==Links== <br />
* The EDA wiki with lots of information on the ETHZ ASIC design flow (internal only) [http://eda.ee.ethz.ch/]<br />
* The IIS/DZ coding guidelines [http://eda.ee.ethz.ch/index.php/Naming_Conventions]<br />
<br />
[[Category:Processor]]<br />
[[Category:Computer Architecture]]<br />
[[Category:Digital]] <br />
[[Category:Security]]<br />
[[Category:PULP]]<br />
[[Category:FPGA]] <br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:HOT]] <br />
<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
[[Category:Digital]]<br />
[[Category:Analog]]<br />
[[Category:Nano-TCAD]]<br />
[[Category:Nano Electronics]]<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Hot]]<br />
<br />
TYPE OF WORK<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
[[Category:Research]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:UltrasoundToGo]]<br />
[[Category:IcySoC]]<br />
[[Category:PSocrates]]<br />
[[Category:UlpSoC]]<br />
[[Category:Qcrypt]]<br />
<br />
YEAR (IF FINISHED)<br />
[[Category:2010]]<br />
[[Category:2011]]<br />
[[Category:2012]]<br />
[[Category:2013]]<br />
[[Category:2014]]<br />
<br />
---></div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=File:Timing_channels_intel.png&diff=4548File:Timing channels intel.png2019-01-31T10:25:40Z<p>Schaffner: Plots taken from http://ts.data61.csiro.au/projects/TS/timingchannels/arch-mitigation.pml</p>
<hr />
<div>Plots taken from http://ts.data61.csiro.au/projects/TS/timingchannels/arch-mitigation.pml</div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=Timing_Channel_Mitigations_for_RISC-V_Cores&diff=4547Timing Channel Mitigations for RISC-V Cores2019-01-31T10:24:36Z<p>Schaffner: Created page with "==Introduction== [timing_channels_intel.png|right|These two ''timing channel matrices'' of a Haswell class Intel processor show the conditional probability of observing an out..."</p>
<hr />
<div>==Introduction==<br />
[timing_channels_intel.png|right|These two ''timing channel matrices'' of a Haswell class Intel processor show the conditional probability of observing an output symbol (vertical axis) given an input symbol (horizontal axis). The effect of timing mitigation techniques can be clearly observed in the right matrix, where almost no correlation can be observed anymore. Images taken from [http://ts.data61.csiro.au/projects/TS/timingchannels/arch-mitigation.pml].]]<br />
<br />
<br />
==Project description==<br />
<br />
The purpose of this project is to get the [http://nvdla.org/ NVIDIA Deep Learning Accelerator] up and running, implement it in a modern ASIC technology node, and compare it against other accelerators in the PULP project. More specifically we would like to see as a result of this project how NVDLA<br />
<br />
* compares against NTX [Schuiki2018], a streaming floating-point accelerator<br />
* compares against Ara, a vector processor based on the RISC-V Vector extension<br />
* compares against RI5CY cluster/Ariane [Gautschi2017,Zaruba2018], two scalar RISC-V processors<br />
<br />
in terms of performance, area, and power consumption. This includes getting familiar with NVDLA, understanding its programming model, and being able to launch computation on it. Since NVDLA is a large unit, we are also interested to see if and how it can be combined with PULP and what scale such a combination would be beneficial. The difference of scales will make it necessary to consider multiple NTX/Ara/RI5CY clusters/Ariane working in tandem in order to attain meaningful comparisons (such as same-compute, same-area, same-power, same-bandwidth settings).<br />
<br />
NVDLA is released as Verilog source code, and all PULP-related sources are in SystemVerilog and VHDL. It is essential that you know or are willing to learn your way around an HDL and ASIC implementation tools (see next section). As a first step we are interested in synthesis results only, but depending on the project's progress we can also consider doing place-and-route to get a feeling how NVDLA behaves in the backend.<br />
<br />
==Required Skills==<br />
To work on this project, you will need:<br />
* to have worked in the past with at least one RTL language (SystemVerilog or Verilog or VHDL) -- having followed the VLSI1 / VLSI2 courses is recommended<br />
* to have prior knowledge of hardware design and computer architecture -- having followed the "Advanced System-on-Chip Design" or "Energy-Efficient Parallel Computing Systems for Data Analytics" course is recommended<br />
<br />
Other skills that you might find useful include:<br />
* familiarity with git, the UNIX shell, C programming<br />
* familiarity with basic system security principles<br />
<br />
===Status: Available ===<br />
: Looking for a Semester Thesis student<br />
: Supervision: [[:User:Schaffner|Michael Schaffner]] [[:User:Zarubaf|Florian Zaruba]] [[:User:Scmoritz|Moritz Schneider]]<br />
<br />
===Professors===<br />
: [https://www.ee.ethz.ch/the-department/people-a-z/person-detail.html?persid=194234 Luca Benini, ETH Zurich]<br />
: [http://ts.data61.csiro.au/people/?cn=Gernot+Heiser Gernot Heiser, UNSW, Sydney]<br />
<br />
==Practical Details==<br />
<br />
TBD<br />
<br />
===Meetings & Presentations===<br />
The students and advisor(s) agree on weekly meetings to discuss all relevant decisions and decide on how to proceed. Of course, additional meetings can be organized to address urgent issues. <br />
<br />
At the end of the project, you have to present/defend your work during a 15 min. presentation and 5 min. of discussion as part of the IIS colloquium.<br />
<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Resources==<br />
* [arianeGit] Ariane is a 6-stage, single issue, in-order CPU which implements the 64-bit RISC-V instruction set [https://github.com/pulp-platform/ariane]<br />
* [Zaruba2018] Zaruba, Florian "Ariane: An open-source 64-bit RISC-V Application-Class Processor and latest Improvements" [https://content.riscv.org/wp-content/uploads/2018/05/14.15-14.40-FlorianZaruba_riscv_workshop-1.pdf]<br />
* [data61timing] Gernot Heiser, et al. "Mitigating microarchitectural timing channels with hardware-provided operations" [http://ts.data61.csiro.au/projects/TS/timingchannels/arch-mitigation.pml]<br />
* [Ge2018a] Ge, Qian et al. "No Security Without Time Protection: We Need a New Hardware-Software Contract." [https://ts.data61.csiro.au/publications/csiro_full_text//Ge_YH_18.pdf]<br />
* [Ge2018b] Ge, Qian et al. "Time Protection: the Missing OS Abstraction." [https://ts.data61.csiro.au/publications/papers/Ge_YCH_18_1.pdf]<br />
<br />
==Links== <br />
* The EDA wiki with lots of information on the ETHZ ASIC design flow (internal only) [http://eda.ee.ethz.ch/]<br />
* The IIS/DZ coding guidelines [http://eda.ee.ethz.ch/index.php/Naming_Conventions]<br />
<br />
[[Category:Processor]]<br />
[[Category:Computer Architecture]]<br />
[[Category:Digital]] <br />
[[Category:Security]]<br />
[[Category:PULP]]<br />
[[Category:FPGA]] <br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:HOT]] <br />
<br />
<!-- <br />
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COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
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[[Category:Digital]]<br />
[[Category:Analog]]<br />
[[Category:Nano-TCAD]]<br />
[[Category:Nano Electronics]]<br />
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STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Hot]]<br />
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TYPE OF WORK<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
[[Category:Research]]<br />
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NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:UltrasoundToGo]]<br />
[[Category:IcySoC]]<br />
[[Category:PSocrates]]<br />
[[Category:UlpSoC]]<br />
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YEAR (IF FINISHED)<br />
[[Category:2010]]<br />
[[Category:2011]]<br />
[[Category:2012]]<br />
[[Category:2013]]<br />
[[Category:2014]]<br />
<br />
---></div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=Accelerator_for_Boosted_Binary_Features&diff=2941Accelerator for Boosted Binary Features2017-08-19T09:51:57Z<p>Schaffner: </p>
<hr />
<div>[[File:FeatureExtractionSystem.jpg|thumb|500px|Current feature extraction system.]]<br />
==Short Description==<br />
Image feature extraction is an important analysis tool in many computer vision applications. In the context of this project, it is specifically used for sparse depth<br />
estimation in stereo video, and sparse flow estimation in normal video. This project builds upon a previous Semester Thesis ([[Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment]]), <br />
where a hardware architecture for image feature extraction has been developed. This IP is currently used in the video analysis part of a more complex video processing system which performs [[Real-Time_Stereo_to_Multiview_Conversion|automatic multiview conversion]] in real-time.<br />
<br />
The goal of this project is now to extend the existing hardware architecture with a new type of descriptor which has recently been developed at the IIS.<br />
This new descriptor uses a different set of low-level features which have been trained using the AdaBoost learning algorithm, and compared to other <br />
standard algorithms it shows much better performance - at relatively low computational cost. <br />
===Status: Completed ===<br />
: Scope: Semester or Master Thesis<br />
: Looking for 1-2 Interested Students<br />
: Supervisors: [[:User:schaffner|Michael Schaffner]], [[:User:Phager | Pascal Hager]]<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: Introductory course in computer vision (recommended)<br />
: Interest in computer graphics / computer vision<br />
: Matlab, VHDL and C++<br />
<br />
===Character===<br />
: 25% Theory & Literature Study<br />
: 35% Matlab Evaluations<br />
: 40% Hw Architecture & FPGA Implementation<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang] ---><br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
===Partners===<br />
: [http://www.disneyresearch.com/research-labs/disney-research-zurich Disney Research Zurich]<br />
<br />
[[#top|↑ top]]<br />
<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
----<br />
<br />
[[#top|↑ top]]<br />
[[Category:Image and Video Processing]] [[Category:Digital]] [[Category:Research]] [[Category:Master Thesis]] [[Category:Semester Thesis]] [[Category:completed]] [[Category:FPGA]] [[Category:2016]]</div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=Accelerator_for_Boosted_Binary_Features&diff=2940Accelerator for Boosted Binary Features2017-08-19T09:51:41Z<p>Schaffner: </p>
<hr />
<div>[[File:FeatureExtractionSystem.jpg|thumb|500px|Current feature extraction system.]]<br />
==Short Description==<br />
Image feature extraction is an important analysis tool in many computer vision applications. In the context of this project, it is specifically used for sparse depth<br />
estimation in stereo video, and sparse flow estimation in normal video. This project builds upon a previous Semester Thesis ([[Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment]]), <br />
where a hardware architecture for image feature extraction has been developed. This IP is currently used in the video analysis part of a more complex video processing system which performs [[Real-Time_Stereo_to_Multiview_Conversion|automatic multiview conversion]] in real-time.<br />
<br />
The goal of this project is now to extend the existing hardware architecture with a new type of descriptor which has recently been developed at the IIS.<br />
This new descriptor uses a different set of low-level features which have been trained using the AdaBoost learning algorithm, and compared to other <br />
standard algorithms it shows much better performance - at relatively low computational cost. <br />
===Status: Completed ===<br />
: Scope: Semester or Master Thesis<br />
: Looking for 1-2 Interested Students<br />
: Supervisors: [[:User:schaffner|Michael Schaffner]], [[:User:Phager | Pascal Hager]]<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: Introductory course in computer vision (recommended)<br />
: Interest in computer graphics / computer vision<br />
: Matlab, VHDL and C++<br />
<br />
===Character===<br />
: 25% Theory & Literature Study<br />
: 35% Matlab Evaluations<br />
: 40% Hw Architecture & FPGA Implementation<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang] ---><br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
===Partners===<br />
: [http://www.disneyresearch.com/research-labs/disney-research-zurich Disney Research Zurich]<br />
<br />
[[#top|↑ top]]<br />
<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
----<br />
<br />
[[#top|↑ top]]<br />
[[Category:Image and Video Processing]] [[Category:Digital]] [[Category:Research]] [[Category:Master Thesis]] [[Category:Semester Thesis]] [[Category:completed]] [[Category:FPGA]] [[Category:Year 2016]]</div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=Accelerator_for_Boosted_Binary_Features&diff=2939Accelerator for Boosted Binary Features2017-08-19T09:47:07Z<p>Schaffner: /* Status: Completed */</p>
<hr />
<div>[[File:FeatureExtractionSystem.jpg|thumb|500px|Current feature extraction system.]]<br />
==Short Description==<br />
Image feature extraction is an important analysis tool in many computer vision applications. In the context of this project, it is specifically used for sparse depth<br />
estimation in stereo video, and sparse flow estimation in normal video. This project builds upon a previous Semester Thesis ([[Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment]]), <br />
where a hardware architecture for image feature extraction has been developed. This IP is currently used in the video analysis part of a more complex video processing system which performs [[Real-Time_Stereo_to_Multiview_Conversion|automatic multiview conversion]] in real-time.<br />
<br />
The goal of this project is now to extend the existing hardware architecture with a new type of descriptor which has recently been developed at the IIS.<br />
This new descriptor uses a different set of low-level features which have been trained using the AdaBoost learning algorithm, and compared to other <br />
standard algorithms it shows much better performance - at relatively low computational cost. <br />
===Status: Completed ===<br />
: Scope: Semester or Master Thesis<br />
: Looking for 1-2 Interested Students<br />
: Supervisors: [[:User:schaffner|Michael Schaffner]], [[:User:Phager | Pascal Hager]]<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: Introductory course in computer vision (recommended)<br />
: Interest in computer graphics / computer vision<br />
: Matlab, VHDL and C++<br />
<br />
===Character===<br />
: 25% Theory & Literature Study<br />
: 35% Matlab Evaluations<br />
: 40% Hw Architecture & FPGA Implementation<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang] ---><br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
===Partners===<br />
: [http://www.disneyresearch.com/research-labs/disney-research-zurich Disney Research Zurich]<br />
<br />
[[#top|↑ top]]<br />
<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
----<br />
<br />
[[#top|↑ top]]<br />
[[Category:Image and Video Processing]] [[Category:Digital]] [[Category:Research]] [[Category:Master Thesis]] [[Category:Semester Thesis]] [[Category:completed]] [[Category:FPGA]]</div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=User:Schaffner&diff=2766User:Schaffner2017-06-01T10:42:47Z<p>Schaffner: </p>
<hr />
<div>==Michael Schaffner==<br />
Michael Schaffner received his M.Sc. degree from the Swiss Federal Institute of Technology Zurich (ETHZ), Switzerland, where he is currently pursuing the Ph.D. degree. Since 2012, he has been a research assistant with the Integrated Systems Laboratory at ETHZ and Disney Research Zurich. His research interests include digital signal processing, stereoscopic video processing and the design of real-time video circuits and systems. He received the ETH-Medal for his master thesis in 2013. <br />
==Interests==<br />
* Digital circuit and system design (FPGA/ASIC)<br />
* Digital signal processing<br />
* Audio / Video processing <br />
==Available Projects==<br />
<br />
==Contact Information==<br />
* '''Office''': ETZ J89<br />
* '''e-mail''': [mailto:schaffner@iis.ee.ethz.ch schaffner@iis.ee.ethz.ch]<br />
* '''phone''': (+41 44 63) 265 56<br />
* '''www''': [http://www.iis.ee.ethz.ch/~michscha http://www.iis.ee.ethz.ch/~michscha]<br />
[[Category:Supervisors]]</div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=User:Schaffner&diff=2765User:Schaffner2017-06-01T10:42:32Z<p>Schaffner: </p>
<hr />
<div>==Michael Schaffner==<br />
Michael Schaffner received his M.Sc. degree from the Swiss Federal Institute of Technology Zurich (ETHZ), Switzerland, where he is currently pursuing the Ph.D. degree. Since 2012, he has been a research assistant with the Integrated Systems Laboratory at ETHZ and Disney Research Zurich. His research interests include digital signal processing, stereoscopic video processing and the design of real-time video circuits and systems. He received the ETH-Medal for his master thesis in 2013. <br />
==Interests==<br />
* Digital circuit and system design (FPGA/ASIC)<br />
* Digital signal processing<br />
* Audio / Video processing <br />
==Available Projects==<br />
<DynamicPageList><br />
supresserrors = true<br />
</DynamicPageList><br />
==Contact Information==<br />
* '''Office''': ETZ J89<br />
* '''e-mail''': [mailto:schaffner@iis.ee.ethz.ch schaffner@iis.ee.ethz.ch]<br />
* '''phone''': (+41 44 63) 265 56<br />
* '''www''': [http://www.iis.ee.ethz.ch/~michscha http://www.iis.ee.ethz.ch/~michscha]<br />
[[Category:Supervisors]]</div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=Accelerator_for_Boosted_Binary_Features&diff=2764Accelerator for Boosted Binary Features2017-06-01T10:41:36Z<p>Schaffner: </p>
<hr />
<div>[[File:FeatureExtractionSystem.jpg|thumb|500px|Current feature extraction system.]]<br />
==Short Description==<br />
Image feature extraction is an important analysis tool in many computer vision applications. In the context of this project, it is specifically used for sparse depth<br />
estimation in stereo video, and sparse flow estimation in normal video. This project builds upon a previous Semester Thesis ([[Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment]]), <br />
where a hardware architecture for image feature extraction has been developed. This IP is currently used in the video analysis part of a more complex video processing system which performs [[Real-Time_Stereo_to_Multiview_Conversion|automatic multiview conversion]] in real-time.<br />
<br />
The goal of this project is now to extend the existing hardware architecture with a new type of descriptor which has recently been developed at the IIS.<br />
This new descriptor uses a different set of low-level features which have been trained using the AdaBoost learning algorithm, and compared to other <br />
standard algorithms it shows much better performance - at relatively low computational cost. <br />
===Status: Available ===<br />
: Scope: Semester or Master Thesis<br />
: Looking for 1-2 Interested Students<br />
: Supervisors: [[:User:schaffner|Michael Schaffner]], [[:User:Phager | Pascal Hager]]<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: Introductory course in computer vision (recommended)<br />
: Interest in computer graphics / computer vision<br />
: Matlab, VHDL and C++<br />
<br />
===Character===<br />
: 25% Theory & Literature Study<br />
: 35% Matlab Evaluations<br />
: 40% Hw Architecture & FPGA Implementation<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang] ---><br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
===Partners===<br />
: [http://www.disneyresearch.com/research-labs/disney-research-zurich Disney Research Zurich]<br />
<br />
[[#top|↑ top]]<br />
<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
----<br />
<br />
[[#top|↑ top]]<br />
[[Category:Image and Video Processing]] [[Category:Digital]] [[Category:Research]] [[Category:Master Thesis]] [[Category:Semester Thesis]] [[Category:completed]] [[Category:FPGA]]</div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=Accelerator_for_Spatio-Temporal_Video_Filtering&diff=2763Accelerator for Spatio-Temporal Video Filtering2017-06-01T10:40:49Z<p>Schaffner: </p>
<hr />
<div>[[File:spt_filtering.jpg|thumb|400px|Spatio temporal filtering example where sparse flow vectors are converted to a dense flow-field ([http://www.disneyresearch.com/wp-content/uploads/Practical-Temporal-Consistency-for-Image-Based-Graphics-Applications-Paper.pdf from]).]]<br />
==Short Description==<br />
There are many image and video processing algorithms (e.g. calculation of Optical-Flow, or Image Domain Warps) that are usually solved using large optimization problems. The solution of such <br />
large optimization problems in real-time is difficult and sometimes even unfeasible. However, the mathematical structure of some of these problems allows us to approximate their solution by using<br />
non-linear filtering in the spatial and temporal domain. These filters scale better in terms of computational complexity than the corresponding optimization problems, and therefore would <br />
allow to perform certain video processing steps more efficiently. <br />
<br />
In this project, we would like to implement the core parts of an efficient STEA filtering algorithm which has recently been developed in collaboration with [http://www.disneyresearch.com/research-labs/disney-research-zurich Disney Research Zurich].<br />
<br />
===Status: In Progress===<br />
: Scope: Semester or Master Thesis<br />
: Looking for 1-2 Interested Students<br />
: Supervisors: [[:User:schaffner|Michael Schaffner]], [[:User:Lukasc|Lukas Cavigelli]]<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: Introductory course in computer vision (optional)<br />
: Interest in computer graphics / computer vision<br />
: Matlab, VHDL and C++<br />
<br />
===Character===<br />
: 10% Theory & Literature Study<br />
: 20% Evaluations<br />
: 70% Hw Architecture & ASIC Implementation<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang] ---><br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
===Partners===<br />
: [http://www.disneyresearch.com/research-labs/disney-research-zurich Disney Research Zurich]<br />
<br />
[[#top|↑ top]]<br />
<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
----<br />
<br />
[[#top|↑ top]]<br />
[[Category:Image and Video Processing]] [[Category:Digital]] [[Category:Research]] [[Category:Master Thesis]] [[Category:Semester Thesis]] [[Category:Hot]] [[Category:Completed]] [[Category:ASIC]][[Category:FPGA]] [[Category:FPGA]] [[Category:2016]]</div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=Accelerator_for_Spatio-Temporal_Video_Filtering&diff=2762Accelerator for Spatio-Temporal Video Filtering2017-06-01T10:40:36Z<p>Schaffner: </p>
<hr />
<div>[[File:spt_filtering.jpg|thumb|400px|Spatio temporal filtering example where sparse flow vectors are converted to a dense flow-field ([http://www.disneyresearch.com/wp-content/uploads/Practical-Temporal-Consistency-for-Image-Based-Graphics-Applications-Paper.pdf from]).]]<br />
==Short Description==<br />
There are many image and video processing algorithms (e.g. calculation of Optical-Flow, or Image Domain Warps) that are usually solved using large optimization problems. The solution of such <br />
large optimization problems in real-time is difficult and sometimes even unfeasible. However, the mathematical structure of some of these problems allows us to approximate their solution by using<br />
non-linear filtering in the spatial and temporal domain. These filters scale better in terms of computational complexity than the corresponding optimization problems, and therefore would <br />
allow to perform certain video processing steps more efficiently. <br />
<br />
In this project, we would like to implement the core parts of an efficient STEA filtering algorithm which has recently been developed in collaboration with [http://www.disneyresearch.com/research-labs/disney-research-zurich Disney Research Zurich].<br />
<br />
===Status: In Progress===<br />
: Scope: Semester or Master Thesis<br />
: Looking for 1-2 Interested Students<br />
: Supervisors: [[:User:schaffner|Michael Schaffner]], [[:User:Lukasc|Lukas Cavigelli]]<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: Introductory course in computer vision (optional)<br />
: Interest in computer graphics / computer vision<br />
: Matlab, VHDL and C++<br />
<br />
===Character===<br />
: 10% Theory & Literature Study<br />
: 20% Evaluations<br />
: 70% Hw Architecture & ASIC Implementation<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang] ---><br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
===Partners===<br />
: [http://www.disneyresearch.com/research-labs/disney-research-zurich Disney Research Zurich]<br />
<br />
[[#top|↑ top]]<br />
<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
----<br />
<br />
[[#top|↑ top]]<br />
[[Category:Image and Video Processing]] [[Category:Digital]] [[Category:Research]] [[Category:Master Thesis]] [[Category:Semester Thesis]] [[Category:Lukasc]] [[Category:Hot]] [[Category:Completed]] [[Category:ASIC]][[Category:FPGA]] [[Category:FPGA]] [[Category:2016]]</div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=Efficient_Implementation_of_an_Active-Set_QP_Solver_for_FPGAs&diff=2761Efficient Implementation of an Active-Set QP Solver for FPGAs2017-06-01T10:39:50Z<p>Schaffner: </p>
<hr />
<div>[[File:teaserAbb.png|400px|right]]<br />
<br />
==Short Description==<br />
Quadratic programming (QP) problems arise in various embedded optimization applications such as model predictive control or constrained least-square fitting. Various solution algorithms have been proposed and implemented on CPUs (some of them also on FPGAs), each of them exhibiting specific advantages and drawbacks. Active-set methods are frequently used on CPUs for solving QPs efficiently, but it is challenging to implement them on FPGAs since they make use of more involved linear algebra operations such as matrix factorizations.<br />
<br />
In this master project you will be working on an efficient FPGA implementation of an online active-set method [1]. The project is a continuation of a [http://iis-projects.ee.ethz.ch/index.php/Active-Set_QP_Solver_on_FPGA past master thesis], and has the following goals:<br />
<br />
* ''Solver improvements'': One of the main tasks will be to analyze and improve the existing implementation. The current solution has been implemented using C++ and Vivado HLS, a high-level synthesis tool for Xilinx FPGAs. The solver is functional, but exhibits a couple of bottlenecks which are due to suboptimal operation scheduling and high-latency operators like FP dividers. We are going to investigate whether the algorithm can be restructured in order to improve the schedule. Also, we are going to look into optimizations and approximations of the employed FP arithmetic in order to improve the latency of certain critical operations.<br />
<br />
* ''Verification and performance assessment'': The solver shall be tested using various QP problems with different dimensions in order to verify the design and get realistic runtime estimates.<br />
<br />
* ''System integration'': Depending on the project progress, we can also start looking into system integration aspects. Eventually, the goal is to attach the developed accelerator to the ARM processing system on the Xilinx Zynq platform, and establish the corresponding software interface.<br />
<br />
This master thesis will be carried out in collaboration with [http://www.abb.ch/cawp/abbzh254/ec72bb280fd24d47c1256b5700522f3a.aspx ABB CHCRC].<br />
<br />
[1] Ferreau, Hans Joachim. "An online active set strategy for fast solution of parametric quadratic programs with applications to predictive engine control." University of Heidelberg (2006).<br />
<br />
===Status: Available ===<br />
: Looking for Interested Students<br />
: Type: Master Thesis<br />
: Supervisors: [[:User:schaffner|Michael Schaffner]], [[:User:Barandre|Andrea Bartolini]]<br />
<br />
===Prerequisites===<br />
: VLSI I, VLSI II, Control Systems<br />
: Matlab, C++, VHDL or System Verilog<br />
<br />
===Character===<br />
: 20% Theory<br />
: 60% Implementation<br />
: 20% Testing<br />
<br />
===Partners===<br />
: [http://www.abb.ch/cawp/abbzh254/ec72bb280fd24d47c1256b5700522f3a.aspx ABB Corporate Research Center (CHCRC)]<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang] ---><br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
[[#top|↑ top]]<br />
<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
<br />
[[Category:Digital]] [[Category:Master Thesis]] [[Category:Accelerator]] [[Category:FPGA]] [[Category:ABB CHCRC]] [[Category:Model Predictive Controller]] [[Category: 2015]]</div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=LAPACK/BLAS_for_FPGA&diff=2760LAPACK/BLAS for FPGA2017-06-01T10:38:53Z<p>Schaffner: </p>
<hr />
<div>[[File:teaserAbb.png|400px|right]]<br />
<br />
==Short Description==<br />
The master thesis will be carry on in collaboration with [http://www.abb.ch/cawp/abbzh254/ec72bb280fd24d47c1256b5700522f3a.aspx ABB CHCRC] and will focus on the acceleration of specific LAPACK/BLAS kernels on FPGA.<br />
<br />
The LAPACK and BLAS libraries have been developed decades ago to perform standard linear algebra operations in an efficient and reliable way. Aim of this thesis is to identify a subset of these routines that are naturally suited to be executed on an FPGA. Out of this subset, a few simple operations are to be implemented on an FPGA, while the implementation is generic enough to take into account actual problem data size as well as resource constraints imposed by the actual FPGA hardware.<br />
<br />
===Status: Available ===<br />
: Looking for Interested Students<br />
: Type: Master- or Semester Thesis<br />
: Supervisors: [[:User:Barandre|Andrea Bartolini]], [[:User:schaffner|Michael Schaffner]]<br />
<br />
===Prerequisites===<br />
: VLSI I, VLSI II<br />
: Matlab, C++, VHDL or System Verilog<br />
<br />
===Character===<br />
: 20% Theory<br />
: 60% Implementation<br />
: 20% Testing<br />
<br />
===Partners===<br />
: [http://www.abb.ch/cawp/abbzh254/ec72bb280fd24d47c1256b5700522f3a.aspx ABB Corporate Research Center (CHCRC)]<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang] ---><br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
[[#top|↑ top]]<br />
<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
<br />
[[[Category:Digital]] [[Category:Master Thesis]] [[Category:Accelerator]] [[Category:FPGA]] [[Category:ABB CHCRC]] [[Category:Model Predictive Controller]] [[Category:least-square fitting]]</div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=Sensor_Fusion_for_Rockfall_Sensor_Node&diff=2524Sensor Fusion for Rockfall Sensor Node2016-11-06T11:46:45Z<p>Schaffner: </p>
<hr />
<div>[[File:stoneNodeFieldTests.jpg|600px|right|thumb]]<br />
[[File:Tramin.jpg|400px|right|thumb]]<br />
[[File:RAMMS_Rockfall.png|400px|right|thumb]]<br />
==Short Description==<br />
Over the last years, [http://www.slf.ch SLF Davos] has been using embedded sensor nodes for measuring trajectories of falling rocks. The acquired data is used to improve simulations of rockfall incidents. However, the employed sensor nodes ([http://www.embedded.arch.ethz.ch/Projects/StoneNode StoneNode]) have come to their end-of-life and are currently being replaced with better and smaller sensors employing state-of-the-art technology. Over the last months, a new StoneNode has been developed at the IIS, and preliminary field test data has recently been obtained.<br />
<br />
In this master project you are going to analyze the obtained data from accelerometers/gyroscopes and pressure sensors, and develop sensor fusion approaches which will allow partial or complete reconstruction of the rock trajectories. Depending on the project progress, novel approaches introducing additional sources of information can be evaluated as well (e.g., videos shot by a drone, 3D terrain models, etc.).<br />
<br />
<br />
===Status: Available ===<br />
* Looking for 1 Master Student<br />
: Supervisors: [[:User:schaffner|Michael Schaffner]], [[:User:lukasc|Lukas Cavigelli]], [[:User:magnom|Michele Magno]], Andrin Caviezel (SLF Davos)<br />
<br />
===Prerequisites===<br />
* Good signal processing background required<br />
* MATLAB, C++ required<br />
* Computer vision course (optional)<br />
<br />
===Character===<br />
: 30% Theory<br />
: 30% Implementation<br />
: 40% Evaluation<br />
<br />
===Partners===<br />
[http://www.slf.ch SLF Davos]<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang] ---><br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
[[#top|↑ top]]<br />
<br />
<!--==Detailed Task Description==---><br />
<!--===Goals===---><br />
<!--===Practical Details===---><br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
[[Category:Digital]]<br />
[[Category:System Software]]<br />
[[Category:Master Thesis]]<br />
[[Category:Hot]]<br />
[[Category:Available]]</div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=Sensor_Fusion_for_Rockfall_Sensor_Node&diff=2523Sensor Fusion for Rockfall Sensor Node2016-11-06T11:46:26Z<p>Schaffner: </p>
<hr />
<div>[[File:stoneNodeFieldTests.jpg|600px|right|thumb]]<br />
[[File:Tramin.jpg|400px|right|thumb]]<br />
[[File:RAMMS_Rockfall.png|400px|right|thumb]]<br />
==Short Description==<br />
Over the last years, [http://www.slf.ch SLF Davos] has been using embedded sensor nodes for measuring trajectories of falling rocks. The acquired data is used to improve simulations of rockfall incidents. However, the employed sensor nodes ([http://www.embedded.arch.ethz.ch/Projects/StoneNode StoneNode]) have come to their end-of-life and are currently being replaced with better and smaller sensors employing state-of-the-art technology. Over the last months, a new StoneNode has been developed at the IIS, and preliminary field test data has recently been obtained.<br />
<br />
In this master project you are going to analyze the obtained data from accelerometers/gyroscopes and pressure sensors, and develop sensor fusion approaches which will allow partial or complete reconstruction of the rock trajectories. Depending on the project progress, novel approaches introducing additional sources of information can be evaluated as well (e.g., videos shot by a drone, 3D terrain models, etc.).<br />
<br />
<br />
===Status: Available ===<br />
* Looking for 1-2 Master Students<br />
: Supervisors: [[:User:schaffner|Michael Schaffner]], [[:User:lukasc|Lukas Cavigelli]], [[:User:magnom|Michele Magno]], Andrin Caviezel (SLF Davos)<br />
<br />
===Prerequisites===<br />
* Good signal processing background required<br />
* MATLAB, C++ required<br />
* Computer vision course (optional)<br />
<br />
===Character===<br />
: 30% Theory<br />
: 30% Implementation<br />
: 40% Evaluation<br />
<br />
===Partners===<br />
[http://www.slf.ch SLF Davos]<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang] ---><br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
[[#top|↑ top]]<br />
<br />
<!--==Detailed Task Description==---><br />
<!--===Goals===---><br />
<!--===Practical Details===---><br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
[[Category:Digital]]<br />
[[Category:System Software]]<br />
[[Category:Master Thesis]]<br />
[[Category:Hot]]<br />
[[Category:Available]]</div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=Sensor_Fusion_for_Rockfall_Sensor_Node&diff=2522Sensor Fusion for Rockfall Sensor Node2016-11-06T11:45:53Z<p>Schaffner: </p>
<hr />
<div>[[File:stoneNodeFieldTests.jpg|600px|right|thumb]]<br />
[[File:Tramin.jpg|400px|right|thumb]]<br />
[[File:RAMMS_Rockfall.png|400px|right|thumb]]<br />
==Short Description==<br />
Over the last years, [http://www.slf.ch SLF Davos] has been using embedded sensor nodes for measuring trajectories of falling rocks. The acquired data is used to improve simulations of rockfall incidents. However, the employed sensor nodes ([http://www.embedded.arch.ethz.ch/Projects/StoneNode StoneNode]) have come to their end-of-life and are currently being replaced with better and smaller sensors employing state-of-the-art technology. Over the last months, a new StoneNode has been developed at the IIS, and preliminary field test data has recently been obtained.<br />
<br />
In this master project you are going to analyze the obtained data from accelerometers/gyroscopes and pressure sensors, and develop sensor fusion approaches which will allow partial or complete reconstruction of the rock trajectories. Depending on the project progress, novel approaches introducing additional sources of information could be evaluated as well (e.g., videos shot by a drone, 3D terrain models, etc.).<br />
<br />
<br />
===Status: Available ===<br />
* Looking for 1-2 Master Students<br />
: Supervisors: [[:User:schaffner|Michael Schaffner]], [[:User:lukasc|Lukas Cavigelli]], [[:User:magnom|Michele Magno]], Andrin Caviezel (SLF Davos)<br />
<br />
===Prerequisites===<br />
* Good signal processing background required<br />
* MATLAB, C++ required<br />
* Computer vision course (optional)<br />
<br />
===Character===<br />
: 30% Theory<br />
: 30% Implementation<br />
: 40% Evaluation<br />
<br />
===Partners===<br />
[http://www.slf.ch SLF Davos]<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang] ---><br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
[[#top|↑ top]]<br />
<br />
<!--==Detailed Task Description==---><br />
<!--===Goals===---><br />
<!--===Practical Details===---><br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
[[Category:Digital]]<br />
[[Category:System Software]]<br />
[[Category:Master Thesis]]<br />
[[Category:Hot]]<br />
[[Category:Available]]</div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=Sensor_Fusion_for_Rockfall_Sensor_Node&diff=2521Sensor Fusion for Rockfall Sensor Node2016-11-06T11:43:33Z<p>Schaffner: </p>
<hr />
<div>[[File:stoneNodeFieldTests.jpg|600px|right|thumb]]<br />
[[File:Tramin.jpg|400px|right|thumb]]<br />
[[File:RAMMS_Rockfall.png|400px|right|thumb]]<br />
==Short Description==<br />
Over the last years, [http://www.slf.ch SLF Davos] has been using embedded sensor nodes for measuring trajectories of falling rocks. The acquired data is used to improve simulations of rockfall incidents. However, the employed sensor nodes ([http://www.embedded.arch.ethz.ch/Projects/StoneNode StoneNode]) have come to their end-of-life and are currently being replaced with better and smaller sensors employing state-of-the-art technology. Over the last months, a new StoneNode has been developed at the IIS, and preliminary field test data has recently been obtained.<br />
<br />
In this master project you are going to analyze the obtained data from accelerometers/gyroscopes and pressure sensors, and develop sensor fusion approaches which will allow partial or complete reconstruction of the rock trajectories. Depending on the project progress, novel approaches introducing additional sources of information could be evaluated as well (e.g., videos shot by a drone, 3D terrain models, etc.).<br />
<br />
<br />
===Status: Available ===<br />
* Looking for 1-2 Master Students<br />
: Supervisors: [[:User:magnom|Michele Magno]], [[:User:schaffner|Michael Schaffner]], [[:User:lukasc|Lukas Cavigelli]], Andrin Caviezel (SLF Davos)<br />
<br />
===Prerequisites===<br />
* PCB design experience (PCB course strongly recommended)<br />
* analog electronics and signal conditioning with operational amplifiers: amplifiers, filters, integrators etc.<br />
* basic knowledge of microcontroller programming (C, preferably Texas Instruments MSP430)<br />
* basic knowledge on signal processing is a plus.<br />
<br />
===Character===<br />
: 30% Theory<br />
: 30% Implementation<br />
: 40% Evaluation<br />
<br />
===Partners===<br />
[http://www.slf.ch SLF Davos]<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang] ---><br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
[[#top|↑ top]]<br />
<br />
<!--==Detailed Task Description==---><br />
<!--===Goals===---><br />
<!--===Practical Details===---><br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
[[Category:Digital]]<br />
[[Category:System Software]]<br />
[[Category:Master Thesis]]<br />
[[Category:Hot]]<br />
[[Category:Available]]</div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=File:StoneNodeFieldTests.jpg&diff=2520File:StoneNodeFieldTests.jpg2016-11-06T11:41:53Z<p>Schaffner: Schaffner uploaded a new version of &quot;File:StoneNodeFieldTests.jpg&quot;</p>
<hr />
<div></div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=Sensor_Fusion_for_Rockfall_Sensor_Node&diff=2519Sensor Fusion for Rockfall Sensor Node2016-11-06T11:40:36Z<p>Schaffner: </p>
<hr />
<div>[[File:stoneNodeFieldTests.jpg|600px|right|thumb]]<br />
[[File:Tramin.jpg|400px|right|thumb]]<br />
[[File:RAMMS_Rockfall.png|400px|right|thumb]]<br />
==Short Description==<br />
Over the last years, [http://www.slf.ch SLF Davos] has been using embedded sensor nodes for measuring trajectories of falling rocks. The acquired data is used to improve simulations of rockfall incidents. However, the employed sensor nodes ([http://www.embedded.arch.ethz.ch/Projects/StoneNode StoneNode]) have come to their end-of-life and are currently being replaced with better and smaller sensors employing state-of-the-art technology. Over the last months, a new StoneNode has been developed at the IIS, and preliminary field test data has recently been obtained.<br />
<br />
In this master project you are going to analyze the obtained data from accelerometers/gyroscopes and pressure sensors, and develop sensor fusion approaches which would allow to partially or completely reconstruct the rock trajectories. Depending on the project progress, novel approaches introducing additional sources of information could be evaluated as well (e.g., videos shot by a drone, 3D terrain models, etc.).<br />
<br />
<br />
===Status: Available ===<br />
* Looking for 1-2 Master Students<br />
: Supervisors: [[:User:magnom|Michele Magno]], [[:User:schaffner|Michael Schaffner]], [[:User:lukasc|Lukas Cavigelli]], Andrin Caviezel (SLF Davos)<br />
<br />
===Prerequisites===<br />
* PCB design experience (PCB course strongly recommended)<br />
* analog electronics and signal conditioning with operational amplifiers: amplifiers, filters, integrators etc.<br />
* basic knowledge of microcontroller programming (C, preferably Texas Instruments MSP430)<br />
* basic knowledge on signal processing is a plus.<br />
<br />
===Character===<br />
: 30% Theory<br />
: 30% Implementation<br />
: 40% Evaluation<br />
<br />
===Partners===<br />
[http://www.slf.ch SLF Davos]<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang] ---><br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
[[#top|↑ top]]<br />
<br />
<!--==Detailed Task Description==---><br />
<!--===Goals===---><br />
<!--===Practical Details===---><br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
[[Category:Digital]]<br />
[[Category:System Software]]<br />
[[Category:Master Thesis]]<br />
[[Category:Hot]]<br />
[[Category:Available]]</div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=File:StoneNodeFieldTests.jpg&diff=2518File:StoneNodeFieldTests.jpg2016-11-06T11:39:59Z<p>Schaffner: </p>
<hr />
<div></div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=Sensor_Fusion_for_Rockfall_Sensor_Node&diff=2517Sensor Fusion for Rockfall Sensor Node2016-11-06T11:39:23Z<p>Schaffner: </p>
<hr />
<div>[[File:stoneNodeTests.jpg|600px|right|thumb]]<br />
[[File:Tramin.jpg|400px|right|thumb]]<br />
[[File:RAMMS_Rockfall.png|400px|right|thumb]]<br />
==Short Description==<br />
Over the last years, [http://www.slf.ch SLF Davos] has been using embedded sensor nodes for measuring trajectories of falling rocks. The acquired data is used to improve simulations of rockfall incidents. However, the employed sensor nodes ([http://www.embedded.arch.ethz.ch/Projects/StoneNode StoneNode]) have come to their end-of-life and are currently being replaced with better and smaller sensors employing state-of-the-art technology. Over the last months, a new StoneNode has been developed at the IIS, and preliminary field test data has recently been obtained.<br />
<br />
In this master project you are going to analyze the obtained data from accelerometers/gyroscopes and pressure sensors, and develop sensor fusion approaches which would allow to partially or completely reconstruct the rock trajectories. Depending on the project progress, novel approaches introducing additional sources of information could be evaluated as well (e.g., videos shot by a drone, 3D terrain models, etc.).<br />
<br />
<br />
===Status: Available ===<br />
* Looking for 1-2 Master Students<br />
: Supervisors: [[:User:magnom|Michele Magno]], [[:User:schaffner|Michael Schaffner]], [[:User:lukasc|Lukas Cavigelli]], Andrin Caviezel (SLF Davos)<br />
<br />
===Prerequisites===<br />
* PCB design experience (PCB course strongly recommended)<br />
* analog electronics and signal conditioning with operational amplifiers: amplifiers, filters, integrators etc.<br />
* basic knowledge of microcontroller programming (C, preferably Texas Instruments MSP430)<br />
* basic knowledge on signal processing is a plus.<br />
<br />
===Character===<br />
: 30% Theory<br />
: 30% Implementation<br />
: 40% Evaluation<br />
<br />
===Partners===<br />
[http://www.slf.ch SLF Davos]<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang] ---><br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
[[#top|↑ top]]<br />
<br />
<!--==Detailed Task Description==---><br />
<!--===Goals===---><br />
<!--===Practical Details===---><br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
[[Category:Digital]]<br />
[[Category:System Software]]<br />
[[Category:Master Thesis]]<br />
[[Category:Hot]]<br />
[[Category:Available]]</div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=Sensor_Fusion_for_Rockfall_Sensor_Node&diff=2516Sensor Fusion for Rockfall Sensor Node2016-11-06T11:36:06Z<p>Schaffner: Created page with "thumb thumb ==Short Description== Over the last years, [http://www.slf.ch SLF Davos] has been using emb..."</p>
<hr />
<div>[[File:Tramin.jpg|400px|right|thumb]]<br />
[[File:RAMMS_Rockfall.png|400px|right|thumb]]<br />
==Short Description==<br />
Over the last years, [http://www.slf.ch SLF Davos] has been using embedded sensor nodes for measuring trajectories of falling rocks. The acquired data is used to improve simulations of rockfall incidents. However, the employed sensor nodes ([http://www.embedded.arch.ethz.ch/Projects/StoneNode StoneNode]) have come to their end-of-life and are currently being replaced with better and smaller sensors employing state-of-the-art technology. Over the last months, a new StoneNode has been developed at the IIS, and preliminary field test data has recently been obtained.<br />
<br />
In this master project you are going to analyze the obtained data from accelerometers/gyroscopes and pressure sensors, and develop sensor fusion approaches which would allow to partially or completely reconstruct the rock trajectories. Depending on the project progress, novel approaches introducing additional sources of information could be evaluated as well (e.g., videos shot by a drone, 3D terrain models, etc.).<br />
<br />
<br />
===Status: Available ===<br />
* Looking for 1-2 Master Students<br />
: Supervisors: [[:User:magnom|Michele Magno]], [[:User:schaffner|Michael Schaffner]], [[:User:lukasc|Lukas Cavigelli]], Andrin Caviezel (SLF Davos)<br />
<br />
===Prerequisites===<br />
* PCB design experience (PCB course strongly recommended)<br />
* analog electronics and signal conditioning with operational amplifiers: amplifiers, filters, integrators etc.<br />
* basic knowledge of microcontroller programming (C, preferably Texas Instruments MSP430)<br />
* basic knowledge on signal processing is a plus.<br />
<br />
===Character===<br />
: 30% Theory<br />
: 30% Implementation<br />
: 40% Evaluation<br />
<br />
===Partners===<br />
[http://www.slf.ch SLF Davos]<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang] ---><br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
[[#top|↑ top]]<br />
<br />
<!--==Detailed Task Description==---><br />
<!--===Goals===---><br />
<!--===Practical Details===---><br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
[[Category:Digital]]<br />
[[Category:System Software]]<br />
[[Category:Master Thesis]]<br />
[[Category:Hot]]<br />
[[Category:Available]]</div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=Image_and_Video_Processing&diff=2515Image and Video Processing2016-11-06T11:26:23Z<p>Schaffner: /* Supervision */</p>
<hr />
<div>[[File:VideoProcessingHeader.jpg]]<br />
<br />
==Available Projects==<br />
We are always looking for students interested in doing a master- or semester project in the field of image and video processing. <br />
Just write us an email or come to our office and then we discuss your interests - even if you don't find a suitable project<br />
in the list below.<br />
<br />
<DynamicPageList><br />
category = Available<br />
category = Image and Video Processing<br />
</DynamicPageList><br />
<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: Introductory course in computer vision (optional)<br />
: Interest in computer graphics / computer vision<br />
: Matlab, VHDL and C++<br />
<br />
===Supervision===<br />
: Supervisors : [[:User:kgf|Frank Gürkaynak]], [[:User:schaffner|Michael Schaffner]], [[:User:lukasc|Lukas Cavigelli]]<br />
: Professor : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang] ---><br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
===Partners===<br />
<br />
Some of these projects are performed in collaboration with [http://www.disneyresearch.com/research-labs/disney-research-zurich Disney Research Zurich].<br />
[[File:Disney_Logo.jpg|200px]]<br />
<br />
==Completed Projects==<br />
These are projects that were completed in the last few years<br />
<br />
===2016===<br />
<DynamicPageList><br />
category = Completed<br />
category = Image and Video Processing<br />
category = 2016<br />
</DynamicPageList><br />
<br />
===2015===<br />
<DynamicPageList><br />
category = Completed<br />
category = Image and Video Processing<br />
category = 2015<br />
</DynamicPageList><br />
<br />
===2014===<br />
<DynamicPageList><br />
category = Completed<br />
category = Image and Video Processing<br />
category = 2014<br />
</DynamicPageList><br />
===2013===<br />
<DynamicPageList><br />
category = Completed<br />
category = Image and Video Processing<br />
category = 2013<br />
</DynamicPageList><br />
===2012===<br />
<DynamicPageList><br />
category = Completed<br />
category = Image and Video Processing<br />
category = 2012<br />
</DynamicPageList><br />
===2011===<br />
<DynamicPageList><br />
category = Completed<br />
category = Image and Video Processing<br />
category = 2011<br />
</DynamicPageList><br />
<br />
----<br />
<br />
[[#top|↑ top]]<br />
[[Category:Digital]] [[Category:Research]] [[Category:Master Thesis]] [[Category:Semester Thesis]] [[Category:Available]] [[Category:FPGA]] [[Category:ASIC]]</div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=Image_and_Video_Processing&diff=2514Image and Video Processing2016-11-06T11:25:42Z<p>Schaffner: /* Completed Projects */</p>
<hr />
<div>[[File:VideoProcessingHeader.jpg]]<br />
<br />
==Available Projects==<br />
We are always looking for students interested in doing a master- or semester project in the field of image and video processing. <br />
Just write us an email or come to our office and then we discuss your interests - even if you don't find a suitable project<br />
in the list below.<br />
<br />
<DynamicPageList><br />
category = Available<br />
category = Image and Video Processing<br />
</DynamicPageList><br />
<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: Introductory course in computer vision (optional)<br />
: Interest in computer graphics / computer vision<br />
: Matlab, VHDL and C++<br />
<br />
===Supervision===<br />
: Supervisors : [[:User:kgf|Frank Gürkaynak]], [[:User:schaffner|Michael Schaffner]]<br />
: Professor : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang] ---><br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
===Partners===<br />
<br />
Some of these projects are performed in collaboration with [http://www.disneyresearch.com/research-labs/disney-research-zurich Disney Research Zurich].<br />
[[File:Disney_Logo.jpg|200px]]<br />
<br />
==Completed Projects==<br />
These are projects that were completed in the last few years<br />
<br />
===2016===<br />
<DynamicPageList><br />
category = Completed<br />
category = Image and Video Processing<br />
category = 2016<br />
</DynamicPageList><br />
<br />
===2015===<br />
<DynamicPageList><br />
category = Completed<br />
category = Image and Video Processing<br />
category = 2015<br />
</DynamicPageList><br />
<br />
===2014===<br />
<DynamicPageList><br />
category = Completed<br />
category = Image and Video Processing<br />
category = 2014<br />
</DynamicPageList><br />
===2013===<br />
<DynamicPageList><br />
category = Completed<br />
category = Image and Video Processing<br />
category = 2013<br />
</DynamicPageList><br />
===2012===<br />
<DynamicPageList><br />
category = Completed<br />
category = Image and Video Processing<br />
category = 2012<br />
</DynamicPageList><br />
===2011===<br />
<DynamicPageList><br />
category = Completed<br />
category = Image and Video Processing<br />
category = 2011<br />
</DynamicPageList><br />
<br />
----<br />
<br />
[[#top|↑ top]]<br />
[[Category:Digital]] [[Category:Research]] [[Category:Master Thesis]] [[Category:Semester Thesis]] [[Category:Available]] [[Category:FPGA]] [[Category:ASIC]]</div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=Image_and_Video_Processing&diff=2513Image and Video Processing2016-11-06T11:25:14Z<p>Schaffner: /* 2015 */</p>
<hr />
<div>[[File:VideoProcessingHeader.jpg]]<br />
<br />
==Available Projects==<br />
We are always looking for students interested in doing a master- or semester project in the field of image and video processing. <br />
Just write us an email or come to our office and then we discuss your interests - even if you don't find a suitable project<br />
in the list below.<br />
<br />
<DynamicPageList><br />
category = Available<br />
category = Image and Video Processing<br />
</DynamicPageList><br />
<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: Introductory course in computer vision (optional)<br />
: Interest in computer graphics / computer vision<br />
: Matlab, VHDL and C++<br />
<br />
===Supervision===<br />
: Supervisors : [[:User:kgf|Frank Gürkaynak]], [[:User:schaffner|Michael Schaffner]]<br />
: Professor : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang] ---><br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
===Partners===<br />
<br />
Some of these projects are performed in collaboration with [http://www.disneyresearch.com/research-labs/disney-research-zurich Disney Research Zurich].<br />
[[File:Disney_Logo.jpg|200px]]<br />
<br />
==Completed Projects==<br />
These are projects that were completed in the last few years<br />
<br />
===2015===<br />
<DynamicPageList><br />
category = Completed<br />
category = Image and Video Processing<br />
category = 2015<br />
</DynamicPageList><br />
<br />
===2014===<br />
<DynamicPageList><br />
category = Completed<br />
category = Image and Video Processing<br />
category = 2014<br />
</DynamicPageList><br />
===2013===<br />
<DynamicPageList><br />
category = Completed<br />
category = Image and Video Processing<br />
category = 2013<br />
</DynamicPageList><br />
===2012===<br />
<DynamicPageList><br />
category = Completed<br />
category = Image and Video Processing<br />
category = 2012<br />
</DynamicPageList><br />
===2011===<br />
<DynamicPageList><br />
category = Completed<br />
category = Image and Video Processing<br />
category = 2011<br />
</DynamicPageList><br />
<br />
----<br />
<br />
[[#top|↑ top]]<br />
[[Category:Digital]] [[Category:Research]] [[Category:Master Thesis]] [[Category:Semester Thesis]] [[Category:Available]] [[Category:FPGA]] [[Category:ASIC]]</div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=Accelerator_for_Boosted_Binary_Features&diff=2512Accelerator for Boosted Binary Features2016-11-06T11:22:59Z<p>Schaffner: </p>
<hr />
<div>[[File:FeatureExtractionSystem.jpg|thumb|500px|Current feature extraction system.]]<br />
==Short Description==<br />
Image feature extraction is an important analysis tool in many computer vision applications. In the context of this project, it is specifically used for sparse depth<br />
estimation in stereo video, and sparse flow estimation in normal video. This project builds upon a previous Semester Thesis ([[Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment]]), <br />
where a hardware architecture for image feature extraction has been developed. This IP is currently used in the video analysis part of a more complex video processing system which performs [[Real-Time_Stereo_to_Multiview_Conversion|automatic multiview conversion]] in real-time.<br />
<br />
The goal of this project is now to extend the existing hardware architecture with a new type of descriptor which has recently been developed at the IIS.<br />
This new descriptor uses a different set of low-level features which have been trained using the AdaBoost learning algorithm, and compared to other <br />
standard algorithms it shows much better performance - at relatively low computational cost. <br />
===Status: Available ===<br />
: Scope: Semester or Master Thesis<br />
: Looking for 1-2 Interested Students<br />
: Supervisors: [[:User:schaffner|Michael Schaffner]], [[:User:Lukasc | Lukas Cavigelli]] <br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: Introductory course in computer vision (recommended)<br />
: Interest in computer graphics / computer vision<br />
: Matlab, VHDL and C++<br />
<br />
===Character===<br />
: 25% Theory & Literature Study<br />
: 35% Matlab Evaluations<br />
: 40% Hw Architecture & FPGA Implementation<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang] ---><br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
===Partners===<br />
: [http://www.disneyresearch.com/research-labs/disney-research-zurich Disney Research Zurich]<br />
<br />
[[#top|↑ top]]<br />
<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
----<br />
<br />
[[#top|↑ top]]<br />
[[Category:Image and Video Processing]] [[Category:Digital]] [[Category:Research]] [[Category:Master Thesis]] [[Category:Semester Thesis]] [[Category:Lukasc]] [[Category:In progress]] [[Category:FPGA]]</div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=Accelerator_for_Spatio-Temporal_Video_Filtering&diff=2511Accelerator for Spatio-Temporal Video Filtering2016-11-06T11:21:38Z<p>Schaffner: </p>
<hr />
<div>[[File:spt_filtering.jpg|thumb|400px|Spatio temporal filtering example where sparse flow vectors are converted to a dense flow-field ([http://www.disneyresearch.com/wp-content/uploads/Practical-Temporal-Consistency-for-Image-Based-Graphics-Applications-Paper.pdf from]).]]<br />
==Short Description==<br />
There are many image and video processing algorithms (e.g. calculation of Optical-Flow, or Image Domain Warps) that are usually solved using large optimization problems. The solution of such <br />
large optimization problems in real-time is difficult and sometimes even unfeasible. However, the mathematical structure of some of these problems allows us to approximate their solution by using<br />
non-linear filtering in the spatial and temporal domain. These filters scale better in terms of computational complexity than the corresponding optimization problems, and therefore would <br />
allow to perform certain video processing steps more efficiently. <br />
<br />
In this project, we would like to implement the core parts of an efficient STEA filtering algorithm which has recently been developed in collaboration with [http://www.disneyresearch.com/research-labs/disney-research-zurich Disney Research Zurich].<br />
<br />
===Status: Available ===<br />
: Scope: Semester or Master Thesis<br />
: Looking for 1-2 Interested Students<br />
: Supervisors: [[:User:schaffner|Michael Schaffner]], [[:User:Lukasc|Lukas Cavigelli]]<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: Introductory course in computer vision (optional)<br />
: Interest in computer graphics / computer vision<br />
: Matlab, VHDL and C++<br />
<br />
===Character===<br />
: 10% Theory & Literature Study<br />
: 20% Evaluations<br />
: 70% Hw Architecture & ASIC Implementation<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang] ---><br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
===Partners===<br />
: [http://www.disneyresearch.com/research-labs/disney-research-zurich Disney Research Zurich]<br />
<br />
[[#top|↑ top]]<br />
<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
----<br />
<br />
[[#top|↑ top]]<br />
[[Category:Image and Video Processing]] [[Category:Digital]] [[Category:Research]] [[Category:Master Thesis]] [[Category:Semester Thesis]] [[Category:Lukasc]] [[Category:Hot]] [[Category:In progress]] [[Category:ASIC]][[Category:FPGA]] [[Category:FPGA]] [[Category:2016]]</div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=PULP&diff=2156PULP2016-05-23T12:31:27Z<p>Schaffner: /* 2016 */</p>
<hr />
<div>__NOTOC__<br />
[[File:pulp_v3_sml.jpg | thumb | 400px | Die micrograph of [http://asic.ethz.ch/2015/Pulpv3.html Pulp v3].]]<br />
<br />
<br />
[[File:pulp_logo_inline2.png| 400px | PULP logo (for different variants and file formats see below)]]<br />
<br />
<br />
<br />
===PULP - An Open Parallel Ultra-Low-Power Processing-Platform===<br />
[[File:pulp_block_diag.png|thumb|400px|Basic block diagram of a PULP system.]]<br />
This is a joint project between the [http://www.iis.ee.ethz.ch Integrated Systems Laboratory (IIS)] of ETH Zurich and the [http://www.dei.unibo.it/en/research/research-facilities/Labs/eess-energy-efficient-embedded-systems Energy-efficient Embedded Systems] (EEES) group of UNIBO to develop an open, scalable Hardware and Software research platform with the goal to break the pJ/op barrier within a power envelope of a few mW.<br />
<br />
The PULP platform is a multi-core platform achieving leading-edge energy-efficiency and featuring widely-tunable performance. The aim of PULP is to satisfy the computational demands of IoT applications requiring flexible processing of data streams generated by multiple sensors, such as accelerometers, low-resolution cameras, microphone arrays, vital signs monitors. As opposed to single-core MCUs, a parallel ultra-low-power programmable architecture allows to meet the computational requirements of these applications, without exceeding the power envelope of a few mW typical of miniaturized, battery-powered systems. Moreover, OpenMP, OpenCL and OpenVX are supported on PULP, enabling agile application porting, development, performance tuning and debugging.<br />
<br />
<br />
[mailto:lbenini@iis.ee.ethz.ch Inquiries] from interested partners are welcome.<br />
<br />
''....more to follow.... stay tuned!''<br />
<br />
See also: <br />
* [http://www.pulp-platform.org Official PULP Project Website]<br />
* [https://github.com/pulp-platform/pulpino PULPino on GitHub] <br />
<br />
<br />
=== PULPino - A Small Single-Core System Based on PULP ===<br />
PULPino is an open-source microcontroller like system, based on a small 32-bit<br />
RISC-V core that was developed at ETH Zurich. The core has an IPC close to 1, full<br />
support for the base integer instruction set (RV32I), compressed instructions<br />
(RV32C) and partial support for the multiplication instruction set<br />
extension (RV32M). It implements our non-standard extensions for hardware<br />
loops, post-incrementing load and store instructions, ALU and MAC<br />
operations.<br />
To allow embedded operating systems such as FreeRTOS to run, a subset of the<br />
privileged specification is supported. When the core is idle, the platform can<br />
be put into a low power mode, where only a simple event unit is active and<br />
wakes up the core in case an event/interrupt arrives.<br />
<br />
The PULPino platform is available for RTL simulation, FPGA and the first ASIC<br />
(called [http://asic.ethz.ch/2015/Imperio.html Imperio]) has been taped out in January 2016. <br />
It has full debug support on all targets. In addition we support extended profiling with source code<br />
annotated execution times through KCacheGrind in RTL simulations.<br />
<br />
PULPino is based on IP blocks from the PULP project. <br />
<br />
<br />
See also: <br />
* [http://www.pulp-platform.org Official PULP Project Website]<br />
* [https://github.com/pulp-platform/pulpino PULPino on GitHub] <br />
* [http://riscv.org/workshop-jan2016/Wed1315%20PULP%20riscv3_noanim.pdf Slides] / [[Media:pulpino_poster_riscv2015.pdf|poster]] from RISC-V Workshop, 2016.<br />
* [https://www.dropbox.com/s/vtrgqnc7dm7gbx2/Andreas%20Traber%20-%20pulpino.pdf?dl=0 Slides] from ORCONF, 2015.<br />
<br />
===Related Available Student Projects===<br />
<br />
<DynamicPageList><br />
category = PULP<br />
category = Available<br />
</DynamicPageList><br />
<br />
<br />
=== [http://asic.ethz.ch/cg/applications/Pulp.html Related Chips] ===<br />
====28nm====<br />
* [http://asic.ethz.ch/2013/Pulp.html Pulp v1] The first version of the PULP platform realized in 28nm FDSOI (RVT) technology with 4 parallel cores. <br />
* [http://asic.ethz.ch/2014/Pulpv2.html Pulp v2] The second version of the PULP platform realized in 28nm FDSOI (LVT) technology with 4 parallel cores.<br />
* [http://asic.ethz.ch/2015/Pulpv3.html Pulp v3] The third version of the PULP platform realized in 28nm FDSOI (RVT) technology with 4 parallel cores and a hardware accelerator.<br />
* [http://asic.ethz.ch/2015/Honey_Bunny.html Honey Bunny] PULp platform using RISC-V compliant RI5CY cores and Globalfoundries 28nm SLP technology. Four cores, 68 kBytes of TCDM and 256 kBytes of L2.<br />
<br />
====65nm====<br />
* [http://asic.ethz.ch/2015/Mia_Wallace.html Mia Wallace] Third generation of PULP platform, HW accelerators, body biasing FLLs, 256 kByte memory <br />
* [http://asic.ethz.ch/2015/Fulmine.html Fulmine] Third generation of PULP platform, Convolutional accelerator, crypto accelerator, body biasing FLLs, 256 kByte memory <br />
* [http://asic.ethz.ch/2014/Artemis.html Artemis] 4 core PULP system including FPU.<br />
* [http://asic.ethz.ch/2014/Hecate.html Hecate] 4 core PULP system with 2 shared FPUs.<br />
* [http://asic.ethz.ch/2014/Selene.html Selene] 4 core PULP system with 1 shared FPU using a logarithmic number system.<br />
* [http://asic.ethz.ch/2014/Diana.html Diana] 4 core PULP system with FPUs designed using approximate computing techniques.<br />
* [http://asic.ethz.ch/2015/Phoebe.html Phoebe] an improved version of [http://asic.ethz.ch/2014/Selene.html Selene], 4 cores and 1 shared vectorial FPU using logarithmic number system<br />
* [http://asic.ethz.ch/2015/Imperio.html Imperio] single core RISC-V based PULPino system. Has the PULP DNA, but is a single core microprocessor complete with peripherals from the PULP project. <br />
====130nm====<br />
* [http://asic.ethz.ch/2015/Vivosoc.html Vivosoc] 2 core mixed-signal PULP system with a low-power A/D converter (130nm)<br />
====180nm====<br />
* [http://asic.ethz.ch/2013/Or10n.html Or10n] An optimized implementation of the OpenRISC processor developed to be used within PULP.<br />
* [http://asic.ethz.ch/2013/Sir10us.html Sir10us] A cryptographic application that uses the Or10n processor developed for PULP.<br />
* [http://asic.ethz.ch/2015/Sid.html Sid] Large PULP chip with in-exact accelerators, LL version<br />
* [http://asic.ethz.ch/2015/Diego.html Diego] Large PULP chip with in-exact accelerators, LVT version <br />
* [http://asic.ethz.ch/2015/Manny.html Manny] Large PULP chip with in-exact accelerators, sub-threshold version<br />
<br />
<br />
===Publications===<br />
<br />
====2016====<br />
<br />
* ''Accuracy and Performance Trade-offs of Logarithmic Number Units in Multi-Core Clusters'', M. Schaffner, M. Gautschi, F. K. Gürkaynak, L. Benini, ARITH, 2016 (to appear)<br />
<br />
* ''PULPino: A small single-core RISC-V SoC'', A. Traber, F. Zaruba, S. Stucki, A. Pullini, G. Haugou, E. Flamand, F. K. Gürkaynak, L. Benini, RISC-V Workshop, 2016, [http://riscv.org/workshop-jan2016/Wed1315%20PULP%20riscv3_noanim.pdf slides], [[Media:pulpino_poster_riscv2015.pdf|poster]]<br />
<br />
* ''Enabling the Heterogeneous Accelerator Model on Ultra-Low Power Microcontroller Platforms'', F. Conti, D. Palossi, A. Marongiu, D. Rossi, L. Benini, DATE, 2016 (to appear)<br />
<br />
* ''High-Efficiency Logarithmic Number Unit Design based on an Improved Cotransformation Scheme'', Y. Popoff, F. Scheidegger, M. Schaffner, M. Gautschi, F. K. Gürkaynak, L. Benini, DATE, 2016 (to appear)<br />
<br />
* ''A 65nm CMOS 6.4-to-29.2pJ/FLOP@0.8V Shared Logarithmic Floating Point Unit for Acceleration of Nonlinear Function Kernels in a Tightly Coupled Processor Cluster'', M. Gautschi, M. Schaffner, F. K. Gürkaynak, L. Benini, ISSCC, 2016, [http://dx.doi.org/10.1109/ISSCC.2016.7417917 paper]<br />
<br />
====2015====<br />
<br />
* ''A Ultra-Low-Energy Convolution Engine for Fast Brain-inspired Vision in Multicore Clusters'', F. Conti, L. Benini, DATE, 2015, [http://dl.acm.org/citation.cfm?id=2755753.2755910 paper]<br />
<br />
* ''Lightweight virtual memory support for many-core accelerators in heterogeneous embedded SoCs'', P. Vogel, A. Marongiu, L. Benini, CODES+ISSS, 2015, [http://dx.doi.org/10.1109/CODESISSS.2015.7331367 paper]<br />
<br />
* ''PULP: OpenRISC-based ultra-low power parallel platform'', D. Rossi, F. Conti, A. Pullini, I. Loi, M. Gautschi, D. Palossi, A. Marongiu, G. Haugou, L. Benini, ORCONF, 2015, [https://www.dropbox.com/s/qs3jbqqiz0948tj/PULP_ORCONF15.pptx?dl=0 slides][https://www.youtube.com/watch?v=HX-QHTMvuzk&list=PLUg3wIOWD8yoX2ECfeU_QP5snbu2Zs1Wp&index=3 video]<br />
<br />
* ''PULPino: A RISC-V based single-core system'', A. Traber, S. Stucki, F. Zaruba, M. Gautschi, A. Pullini, I. Loi, D. Rossi, G. Haugou, F. K. Gürkaynak, L. Benini, ORCONF, 2015, [https://www.dropbox.com/s/vtrgqnc7dm7gbx2/Andreas%20Traber%20-%20pulpino.pdf?dl=0 slides][https://www.youtube.com/watch?v=-_zGoJmPddo&index=4&list=PLUg3wIOWD8yoX2ECfeU_QP5snbu2Zs1Wp video]<br />
<br />
* ''Exploring Multi-banked Shared-L1 Program Cache on Ultra-Low Power Tightly Coupled Processor Clusters'', I. Loi, D. Rossi, G. Haugou, M. Gautschi, L. Benini, ACM Computing Frontiers, 2015, [http://dx.doi.org/10.1145/2742854.2747288 paper]<br />
<br />
* ''PULP: A Ultra-Low Power Parallel Accelerator for Energy-Efficient and Flexible Embedded Vision'', F. Conti, D. Rossi, A. Pullini, I. Loi, L. Benini, Journal of Signal Processing Systems, October 2015, [http://link.springer.com/article/10.1007%2Fs11265-015-1070-9 paper]<br />
<br />
* ''A −1.8V to 0.9V body bias, 60 GOPS/W 4-core cluster in low-power 28nm UTBB FD-SOI technology'', D. Rossi, A. Pullini, M. Gautschi, I. Loi, F.K. Gurkaynak, P. Flatresse, L. Benini, S3S, October 2015, [http://dx.doi.org/10.1109/S3S.2015.7333483 paper]<br />
<br />
* ''A 60 GOPS/W, −1.8 V to 0.9 V body bias ULP cluster in 28 nm UTBB FD-SOI technology'', D. Rossi, A. Pullini, I. Loi, F. K. Gürkaynak, A. Bartolini, P. Flatresse, L. Benini, Solid-State Electronics, 2016, [http://dx.doi.org/10.1016/j.sse.2015.11.015 paper] <br />
<br />
* ''PULP: A Parallel Ultra-Low-Power Platform for Next Generation IoT Applications'', D. Rossi, F. Conti, A. Marongiu, A. Pullini, I. Loi, M. Gautschi, G. Tagliavini, A. Capotondi, P. Flatresse, L. Benini, HOT Chips, 2015, [http://www.hotchips.org/wp-content/uploads/hc_archives/hc27/HC27.24-Monday-Epub/HC27.24.10-IoT-Epub/HC27.24.111-PULP-Rossi-DEL-ETH-2.pdf slides]<br />
<br />
* ''Tailoring instruction-set extensions for an ultra-low power tightly-coupled cluster of OpenRISC cores'', M. Gautschi, A. Traber, A. Pullini, L. Benini, M. Scandale, A. Di Federico, M. Beretta, G. Agosta, VLSI-SoC, 2015, [http://dx.doi.org/10.1109/VLSI-SoC.2015.7314386 paper]<br />
<br />
<br />
====2014====<br />
<br />
* ''Energy-efficient vision on the PULP platform for ultra-low power parallel computing'', F. Conti, D. Rossi, A. Pullini, I. Loi, L. Benini, SiPS, 2014, [http://dx.doi.org/10.1109/SiPS.2014.6986099 paper]<br />
<br />
* ''Ultra-low-latency lightweight DMA for tightly coupled multi-core clusters'', D. Rossi, I. Loi, G. Haugou, L. Benini, ACM Computing Frontiers, 2014, [http://dx.doi.org/10.1145/2597917.2597922 paper]<br />
<br />
* ''Customizing an Open Source Processor to Fit in an Ultra-Low Power Cluster with a Shared L1 Memory'', M. Gautschi, D. Rossi, L. Benini, GLSVLSI, 2014, [http://dx.doi.org/10.1145/2591513.2591569 paper]<br />
<br />
* ''Energy efficient parallel computing on the PULP platform with support for OpenMP'', D. Rossi, I. Loi, F. Conti, G. Tagliavini, A. Pullini, A. Marongiu, IEEEI, 2014, [http://dx.doi.org/10.1109/EEEI.2014.7005803 paper]<br />
<br />
===Links===<br />
* [http://www.pulp-platform.org Official PULP Project Website]<br />
* [https://github.com/pulp-platform/pulpino PULPino on GitHub] <br />
* [http://iis.ee.ethz.ch/~haugoug/pulp PULP SDK] (Software Development Kit)<br />
* [http://www-micrel.deis.unibo.it/pulp-project PULP page in University of Bologna]<br />
* [http://compilergroup.elet.polimi.it/doku.php?id=research:pulp LLVM compiler for PULP developed by Politecnico di Milano] <br />
** [http://compilergroup-srv.elet.polimi.it/toolchains/or1k-toolchain-linux-amd64-latest.tar.gz Latest compiled toolchain for Linux EL6]<br />
<br />
<br />
===Templates and Logos===<br />
[[Media:pulp_logos.tar|This archive]] contains all PULP logos below as well as inverted versions thereof for dark backgrounds (in PDF and PNG formats). Also, it includes the "Orbitron" font which has been used here.<br />
<br />
For documentation, please use the following [[Media:Pulp_ug_template_v1.0.tar.gz|Word template (v1.0)]]. And here is a PULP [[Media:Pulp_slide_template_v1.0.pptx|slide template for Powerpoint (v1.0)]].<br />
<br />
====Inline====<br />
[[File:pulp_logo_inline2.png|250px|Inline PULP logo, variant 2 ([[Media:pulp_logo_inline2.png|PNG]] [[Media:pulp_logo_inline2.pdf|PDF]]).]]<br />
[[File:pulp_logo_inline1.png|250px|Inline PULP logo, variant 1 ([[Media:pulp_logo_inline1.png|PNG]] [[Media:pulp_logo_inline1.pdf|PDF]]).]]<br />
====Big====<br />
[[File:pulp_logo_big2.png|140px|Big PULP logo, variant 2 ([[Media:pulp_logo_big2.png|PNG]] [[Media:pulp_logo_big2.pdf|PDF]]).]]<br />
[[File:pulp_logo_big1.png|140px|Big PULP logo, variant 1 ([[Media:pulp_logo_big1.png|PNG]] [[Media:pulp_logo_big1.pdf|PDF]]).]]<br />
[[File:pulp_logo_icon.png|140px|Main PULP logo icon ([[Media:pulp_logo_icon.png|PNG]] [[Media:pulp_logo_icon.pdf|PDF]]).]] <br />
<br />
[[Category:PULP]]</div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=PULP&diff=2155PULP2016-05-23T12:30:51Z<p>Schaffner: /* 2016 */</p>
<hr />
<div>__NOTOC__<br />
[[File:pulp_v3_sml.jpg | thumb | 400px | Die micrograph of [http://asic.ethz.ch/2015/Pulpv3.html Pulp v3].]]<br />
<br />
<br />
[[File:pulp_logo_inline2.png| 400px | PULP logo (for different variants and file formats see below)]]<br />
<br />
<br />
<br />
===PULP - An Open Parallel Ultra-Low-Power Processing-Platform===<br />
[[File:pulp_block_diag.png|thumb|400px|Basic block diagram of a PULP system.]]<br />
This is a joint project between the [http://www.iis.ee.ethz.ch Integrated Systems Laboratory (IIS)] of ETH Zurich and the [http://www.dei.unibo.it/en/research/research-facilities/Labs/eess-energy-efficient-embedded-systems Energy-efficient Embedded Systems] (EEES) group of UNIBO to develop an open, scalable Hardware and Software research platform with the goal to break the pJ/op barrier within a power envelope of a few mW.<br />
<br />
The PULP platform is a multi-core platform achieving leading-edge energy-efficiency and featuring widely-tunable performance. The aim of PULP is to satisfy the computational demands of IoT applications requiring flexible processing of data streams generated by multiple sensors, such as accelerometers, low-resolution cameras, microphone arrays, vital signs monitors. As opposed to single-core MCUs, a parallel ultra-low-power programmable architecture allows to meet the computational requirements of these applications, without exceeding the power envelope of a few mW typical of miniaturized, battery-powered systems. Moreover, OpenMP, OpenCL and OpenVX are supported on PULP, enabling agile application porting, development, performance tuning and debugging.<br />
<br />
<br />
[mailto:lbenini@iis.ee.ethz.ch Inquiries] from interested partners are welcome.<br />
<br />
''....more to follow.... stay tuned!''<br />
<br />
See also: <br />
* [http://www.pulp-platform.org Official PULP Project Website]<br />
* [https://github.com/pulp-platform/pulpino PULPino on GitHub] <br />
<br />
<br />
=== PULPino - A Small Single-Core System Based on PULP ===<br />
PULPino is an open-source microcontroller like system, based on a small 32-bit<br />
RISC-V core that was developed at ETH Zurich. The core has an IPC close to 1, full<br />
support for the base integer instruction set (RV32I), compressed instructions<br />
(RV32C) and partial support for the multiplication instruction set<br />
extension (RV32M). It implements our non-standard extensions for hardware<br />
loops, post-incrementing load and store instructions, ALU and MAC<br />
operations.<br />
To allow embedded operating systems such as FreeRTOS to run, a subset of the<br />
privileged specification is supported. When the core is idle, the platform can<br />
be put into a low power mode, where only a simple event unit is active and<br />
wakes up the core in case an event/interrupt arrives.<br />
<br />
The PULPino platform is available for RTL simulation, FPGA and the first ASIC<br />
(called [http://asic.ethz.ch/2015/Imperio.html Imperio]) has been taped out in January 2016. <br />
It has full debug support on all targets. In addition we support extended profiling with source code<br />
annotated execution times through KCacheGrind in RTL simulations.<br />
<br />
PULPino is based on IP blocks from the PULP project. <br />
<br />
<br />
See also: <br />
* [http://www.pulp-platform.org Official PULP Project Website]<br />
* [https://github.com/pulp-platform/pulpino PULPino on GitHub] <br />
* [http://riscv.org/workshop-jan2016/Wed1315%20PULP%20riscv3_noanim.pdf Slides] / [[Media:pulpino_poster_riscv2015.pdf|poster]] from RISC-V Workshop, 2016.<br />
* [https://www.dropbox.com/s/vtrgqnc7dm7gbx2/Andreas%20Traber%20-%20pulpino.pdf?dl=0 Slides] from ORCONF, 2015.<br />
<br />
===Related Available Student Projects===<br />
<br />
<DynamicPageList><br />
category = PULP<br />
category = Available<br />
</DynamicPageList><br />
<br />
<br />
=== [http://asic.ethz.ch/cg/applications/Pulp.html Related Chips] ===<br />
====28nm====<br />
* [http://asic.ethz.ch/2013/Pulp.html Pulp v1] The first version of the PULP platform realized in 28nm FDSOI (RVT) technology with 4 parallel cores. <br />
* [http://asic.ethz.ch/2014/Pulpv2.html Pulp v2] The second version of the PULP platform realized in 28nm FDSOI (LVT) technology with 4 parallel cores.<br />
* [http://asic.ethz.ch/2015/Pulpv3.html Pulp v3] The third version of the PULP platform realized in 28nm FDSOI (RVT) technology with 4 parallel cores and a hardware accelerator.<br />
* [http://asic.ethz.ch/2015/Honey_Bunny.html Honey Bunny] PULp platform using RISC-V compliant RI5CY cores and Globalfoundries 28nm SLP technology. Four cores, 68 kBytes of TCDM and 256 kBytes of L2.<br />
<br />
====65nm====<br />
* [http://asic.ethz.ch/2015/Mia_Wallace.html Mia Wallace] Third generation of PULP platform, HW accelerators, body biasing FLLs, 256 kByte memory <br />
* [http://asic.ethz.ch/2015/Fulmine.html Fulmine] Third generation of PULP platform, Convolutional accelerator, crypto accelerator, body biasing FLLs, 256 kByte memory <br />
* [http://asic.ethz.ch/2014/Artemis.html Artemis] 4 core PULP system including FPU.<br />
* [http://asic.ethz.ch/2014/Hecate.html Hecate] 4 core PULP system with 2 shared FPUs.<br />
* [http://asic.ethz.ch/2014/Selene.html Selene] 4 core PULP system with 1 shared FPU using a logarithmic number system.<br />
* [http://asic.ethz.ch/2014/Diana.html Diana] 4 core PULP system with FPUs designed using approximate computing techniques.<br />
* [http://asic.ethz.ch/2015/Phoebe.html Phoebe] an improved version of [http://asic.ethz.ch/2014/Selene.html Selene], 4 cores and 1 shared vectorial FPU using logarithmic number system<br />
* [http://asic.ethz.ch/2015/Imperio.html Imperio] single core RISC-V based PULPino system. Has the PULP DNA, but is a single core microprocessor complete with peripherals from the PULP project. <br />
====130nm====<br />
* [http://asic.ethz.ch/2015/Vivosoc.html Vivosoc] 2 core mixed-signal PULP system with a low-power A/D converter (130nm)<br />
====180nm====<br />
* [http://asic.ethz.ch/2013/Or10n.html Or10n] An optimized implementation of the OpenRISC processor developed to be used within PULP.<br />
* [http://asic.ethz.ch/2013/Sir10us.html Sir10us] A cryptographic application that uses the Or10n processor developed for PULP.<br />
* [http://asic.ethz.ch/2015/Sid.html Sid] Large PULP chip with in-exact accelerators, LL version<br />
* [http://asic.ethz.ch/2015/Diego.html Diego] Large PULP chip with in-exact accelerators, LVT version <br />
* [http://asic.ethz.ch/2015/Manny.html Manny] Large PULP chip with in-exact accelerators, sub-threshold version<br />
<br />
<br />
===Publications===<br />
<br />
====2016====<br />
<br />
* ''Accuracy and Performance Trade-offs of Logarithmic Number Units in Multi-Core Clusters'', M. Schaffner, M. Gautschi, F. K. Gürkaynak, L. Benini, ARITH, 2016<br />
<br />
* ''PULPino: A small single-core RISC-V SoC'', A. Traber, F. Zaruba, S. Stucki, A. Pullini, G. Haugou, E. Flamand, F. K. Gürkaynak, L. Benini, RISC-V Workshop, 2016, [http://riscv.org/workshop-jan2016/Wed1315%20PULP%20riscv3_noanim.pdf slides], [[Media:pulpino_poster_riscv2015.pdf|poster]]<br />
<br />
* ''Enabling the Heterogeneous Accelerator Model on Ultra-Low Power Microcontroller Platforms'', F. Conti, D. Palossi, A. Marongiu, D. Rossi, L. Benini, DATE, 2016 (to appear)<br />
<br />
* ''High-Efficiency Logarithmic Number Unit Design based on an Improved Cotransformation Scheme'', Y. Popoff, F. Scheidegger, M. Schaffner, M. Gautschi, F. K. Gürkaynak, L. Benini, DATE, 2016 (to appear)<br />
<br />
* ''A 65nm CMOS 6.4-to-29.2pJ/FLOP@0.8V Shared Logarithmic Floating Point Unit for Acceleration of Nonlinear Function Kernels in a Tightly Coupled Processor Cluster'', M. Gautschi, M. Schaffner, F. K. Gürkaynak, L. Benini, ISSCC, 2016, [http://dx.doi.org/10.1109/ISSCC.2016.7417917 paper]<br />
<br />
====2015====<br />
<br />
* ''A Ultra-Low-Energy Convolution Engine for Fast Brain-inspired Vision in Multicore Clusters'', F. Conti, L. Benini, DATE, 2015, [http://dl.acm.org/citation.cfm?id=2755753.2755910 paper]<br />
<br />
* ''Lightweight virtual memory support for many-core accelerators in heterogeneous embedded SoCs'', P. Vogel, A. Marongiu, L. Benini, CODES+ISSS, 2015, [http://dx.doi.org/10.1109/CODESISSS.2015.7331367 paper]<br />
<br />
* ''PULP: OpenRISC-based ultra-low power parallel platform'', D. Rossi, F. Conti, A. Pullini, I. Loi, M. Gautschi, D. Palossi, A. Marongiu, G. Haugou, L. Benini, ORCONF, 2015, [https://www.dropbox.com/s/qs3jbqqiz0948tj/PULP_ORCONF15.pptx?dl=0 slides][https://www.youtube.com/watch?v=HX-QHTMvuzk&list=PLUg3wIOWD8yoX2ECfeU_QP5snbu2Zs1Wp&index=3 video]<br />
<br />
* ''PULPino: A RISC-V based single-core system'', A. Traber, S. Stucki, F. Zaruba, M. Gautschi, A. Pullini, I. Loi, D. Rossi, G. Haugou, F. K. Gürkaynak, L. Benini, ORCONF, 2015, [https://www.dropbox.com/s/vtrgqnc7dm7gbx2/Andreas%20Traber%20-%20pulpino.pdf?dl=0 slides][https://www.youtube.com/watch?v=-_zGoJmPddo&index=4&list=PLUg3wIOWD8yoX2ECfeU_QP5snbu2Zs1Wp video]<br />
<br />
* ''Exploring Multi-banked Shared-L1 Program Cache on Ultra-Low Power Tightly Coupled Processor Clusters'', I. Loi, D. Rossi, G. Haugou, M. Gautschi, L. Benini, ACM Computing Frontiers, 2015, [http://dx.doi.org/10.1145/2742854.2747288 paper]<br />
<br />
* ''PULP: A Ultra-Low Power Parallel Accelerator for Energy-Efficient and Flexible Embedded Vision'', F. Conti, D. Rossi, A. Pullini, I. Loi, L. Benini, Journal of Signal Processing Systems, October 2015, [http://link.springer.com/article/10.1007%2Fs11265-015-1070-9 paper]<br />
<br />
* ''A −1.8V to 0.9V body bias, 60 GOPS/W 4-core cluster in low-power 28nm UTBB FD-SOI technology'', D. Rossi, A. Pullini, M. Gautschi, I. Loi, F.K. Gurkaynak, P. Flatresse, L. Benini, S3S, October 2015, [http://dx.doi.org/10.1109/S3S.2015.7333483 paper]<br />
<br />
* ''A 60 GOPS/W, −1.8 V to 0.9 V body bias ULP cluster in 28 nm UTBB FD-SOI technology'', D. Rossi, A. Pullini, I. Loi, F. K. Gürkaynak, A. Bartolini, P. Flatresse, L. Benini, Solid-State Electronics, 2016, [http://dx.doi.org/10.1016/j.sse.2015.11.015 paper] <br />
<br />
* ''PULP: A Parallel Ultra-Low-Power Platform for Next Generation IoT Applications'', D. Rossi, F. Conti, A. Marongiu, A. Pullini, I. Loi, M. Gautschi, G. Tagliavini, A. Capotondi, P. Flatresse, L. Benini, HOT Chips, 2015, [http://www.hotchips.org/wp-content/uploads/hc_archives/hc27/HC27.24-Monday-Epub/HC27.24.10-IoT-Epub/HC27.24.111-PULP-Rossi-DEL-ETH-2.pdf slides]<br />
<br />
* ''Tailoring instruction-set extensions for an ultra-low power tightly-coupled cluster of OpenRISC cores'', M. Gautschi, A. Traber, A. Pullini, L. Benini, M. Scandale, A. Di Federico, M. Beretta, G. Agosta, VLSI-SoC, 2015, [http://dx.doi.org/10.1109/VLSI-SoC.2015.7314386 paper]<br />
<br />
<br />
====2014====<br />
<br />
* ''Energy-efficient vision on the PULP platform for ultra-low power parallel computing'', F. Conti, D. Rossi, A. Pullini, I. Loi, L. Benini, SiPS, 2014, [http://dx.doi.org/10.1109/SiPS.2014.6986099 paper]<br />
<br />
* ''Ultra-low-latency lightweight DMA for tightly coupled multi-core clusters'', D. Rossi, I. Loi, G. Haugou, L. Benini, ACM Computing Frontiers, 2014, [http://dx.doi.org/10.1145/2597917.2597922 paper]<br />
<br />
* ''Customizing an Open Source Processor to Fit in an Ultra-Low Power Cluster with a Shared L1 Memory'', M. Gautschi, D. Rossi, L. Benini, GLSVLSI, 2014, [http://dx.doi.org/10.1145/2591513.2591569 paper]<br />
<br />
* ''Energy efficient parallel computing on the PULP platform with support for OpenMP'', D. Rossi, I. Loi, F. Conti, G. Tagliavini, A. Pullini, A. Marongiu, IEEEI, 2014, [http://dx.doi.org/10.1109/EEEI.2014.7005803 paper]<br />
<br />
===Links===<br />
* [http://www.pulp-platform.org Official PULP Project Website]<br />
* [https://github.com/pulp-platform/pulpino PULPino on GitHub] <br />
* [http://iis.ee.ethz.ch/~haugoug/pulp PULP SDK] (Software Development Kit)<br />
* [http://www-micrel.deis.unibo.it/pulp-project PULP page in University of Bologna]<br />
* [http://compilergroup.elet.polimi.it/doku.php?id=research:pulp LLVM compiler for PULP developed by Politecnico di Milano] <br />
** [http://compilergroup-srv.elet.polimi.it/toolchains/or1k-toolchain-linux-amd64-latest.tar.gz Latest compiled toolchain for Linux EL6]<br />
<br />
<br />
===Templates and Logos===<br />
[[Media:pulp_logos.tar|This archive]] contains all PULP logos below as well as inverted versions thereof for dark backgrounds (in PDF and PNG formats). Also, it includes the "Orbitron" font which has been used here.<br />
<br />
For documentation, please use the following [[Media:Pulp_ug_template_v1.0.tar.gz|Word template (v1.0)]]. And here is a PULP [[Media:Pulp_slide_template_v1.0.pptx|slide template for Powerpoint (v1.0)]].<br />
<br />
====Inline====<br />
[[File:pulp_logo_inline2.png|250px|Inline PULP logo, variant 2 ([[Media:pulp_logo_inline2.png|PNG]] [[Media:pulp_logo_inline2.pdf|PDF]]).]]<br />
[[File:pulp_logo_inline1.png|250px|Inline PULP logo, variant 1 ([[Media:pulp_logo_inline1.png|PNG]] [[Media:pulp_logo_inline1.pdf|PDF]]).]]<br />
====Big====<br />
[[File:pulp_logo_big2.png|140px|Big PULP logo, variant 2 ([[Media:pulp_logo_big2.png|PNG]] [[Media:pulp_logo_big2.pdf|PDF]]).]]<br />
[[File:pulp_logo_big1.png|140px|Big PULP logo, variant 1 ([[Media:pulp_logo_big1.png|PNG]] [[Media:pulp_logo_big1.pdf|PDF]]).]]<br />
[[File:pulp_logo_icon.png|140px|Main PULP logo icon ([[Media:pulp_logo_icon.png|PNG]] [[Media:pulp_logo_icon.pdf|PDF]]).]] <br />
<br />
[[Category:PULP]]</div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=PULP&diff=2154PULP2016-05-23T12:30:26Z<p>Schaffner: /* 2016 */</p>
<hr />
<div>__NOTOC__<br />
[[File:pulp_v3_sml.jpg | thumb | 400px | Die micrograph of [http://asic.ethz.ch/2015/Pulpv3.html Pulp v3].]]<br />
<br />
<br />
[[File:pulp_logo_inline2.png| 400px | PULP logo (for different variants and file formats see below)]]<br />
<br />
<br />
<br />
===PULP - An Open Parallel Ultra-Low-Power Processing-Platform===<br />
[[File:pulp_block_diag.png|thumb|400px|Basic block diagram of a PULP system.]]<br />
This is a joint project between the [http://www.iis.ee.ethz.ch Integrated Systems Laboratory (IIS)] of ETH Zurich and the [http://www.dei.unibo.it/en/research/research-facilities/Labs/eess-energy-efficient-embedded-systems Energy-efficient Embedded Systems] (EEES) group of UNIBO to develop an open, scalable Hardware and Software research platform with the goal to break the pJ/op barrier within a power envelope of a few mW.<br />
<br />
The PULP platform is a multi-core platform achieving leading-edge energy-efficiency and featuring widely-tunable performance. The aim of PULP is to satisfy the computational demands of IoT applications requiring flexible processing of data streams generated by multiple sensors, such as accelerometers, low-resolution cameras, microphone arrays, vital signs monitors. As opposed to single-core MCUs, a parallel ultra-low-power programmable architecture allows to meet the computational requirements of these applications, without exceeding the power envelope of a few mW typical of miniaturized, battery-powered systems. Moreover, OpenMP, OpenCL and OpenVX are supported on PULP, enabling agile application porting, development, performance tuning and debugging.<br />
<br />
<br />
[mailto:lbenini@iis.ee.ethz.ch Inquiries] from interested partners are welcome.<br />
<br />
''....more to follow.... stay tuned!''<br />
<br />
See also: <br />
* [http://www.pulp-platform.org Official PULP Project Website]<br />
* [https://github.com/pulp-platform/pulpino PULPino on GitHub] <br />
<br />
<br />
=== PULPino - A Small Single-Core System Based on PULP ===<br />
PULPino is an open-source microcontroller like system, based on a small 32-bit<br />
RISC-V core that was developed at ETH Zurich. The core has an IPC close to 1, full<br />
support for the base integer instruction set (RV32I), compressed instructions<br />
(RV32C) and partial support for the multiplication instruction set<br />
extension (RV32M). It implements our non-standard extensions for hardware<br />
loops, post-incrementing load and store instructions, ALU and MAC<br />
operations.<br />
To allow embedded operating systems such as FreeRTOS to run, a subset of the<br />
privileged specification is supported. When the core is idle, the platform can<br />
be put into a low power mode, where only a simple event unit is active and<br />
wakes up the core in case an event/interrupt arrives.<br />
<br />
The PULPino platform is available for RTL simulation, FPGA and the first ASIC<br />
(called [http://asic.ethz.ch/2015/Imperio.html Imperio]) has been taped out in January 2016. <br />
It has full debug support on all targets. In addition we support extended profiling with source code<br />
annotated execution times through KCacheGrind in RTL simulations.<br />
<br />
PULPino is based on IP blocks from the PULP project. <br />
<br />
<br />
See also: <br />
* [http://www.pulp-platform.org Official PULP Project Website]<br />
* [https://github.com/pulp-platform/pulpino PULPino on GitHub] <br />
* [http://riscv.org/workshop-jan2016/Wed1315%20PULP%20riscv3_noanim.pdf Slides] / [[Media:pulpino_poster_riscv2015.pdf|poster]] from RISC-V Workshop, 2016.<br />
* [https://www.dropbox.com/s/vtrgqnc7dm7gbx2/Andreas%20Traber%20-%20pulpino.pdf?dl=0 Slides] from ORCONF, 2015.<br />
<br />
===Related Available Student Projects===<br />
<br />
<DynamicPageList><br />
category = PULP<br />
category = Available<br />
</DynamicPageList><br />
<br />
<br />
=== [http://asic.ethz.ch/cg/applications/Pulp.html Related Chips] ===<br />
====28nm====<br />
* [http://asic.ethz.ch/2013/Pulp.html Pulp v1] The first version of the PULP platform realized in 28nm FDSOI (RVT) technology with 4 parallel cores. <br />
* [http://asic.ethz.ch/2014/Pulpv2.html Pulp v2] The second version of the PULP platform realized in 28nm FDSOI (LVT) technology with 4 parallel cores.<br />
* [http://asic.ethz.ch/2015/Pulpv3.html Pulp v3] The third version of the PULP platform realized in 28nm FDSOI (RVT) technology with 4 parallel cores and a hardware accelerator.<br />
* [http://asic.ethz.ch/2015/Honey_Bunny.html Honey Bunny] PULp platform using RISC-V compliant RI5CY cores and Globalfoundries 28nm SLP technology. Four cores, 68 kBytes of TCDM and 256 kBytes of L2.<br />
<br />
====65nm====<br />
* [http://asic.ethz.ch/2015/Mia_Wallace.html Mia Wallace] Third generation of PULP platform, HW accelerators, body biasing FLLs, 256 kByte memory <br />
* [http://asic.ethz.ch/2015/Fulmine.html Fulmine] Third generation of PULP platform, Convolutional accelerator, crypto accelerator, body biasing FLLs, 256 kByte memory <br />
* [http://asic.ethz.ch/2014/Artemis.html Artemis] 4 core PULP system including FPU.<br />
* [http://asic.ethz.ch/2014/Hecate.html Hecate] 4 core PULP system with 2 shared FPUs.<br />
* [http://asic.ethz.ch/2014/Selene.html Selene] 4 core PULP system with 1 shared FPU using a logarithmic number system.<br />
* [http://asic.ethz.ch/2014/Diana.html Diana] 4 core PULP system with FPUs designed using approximate computing techniques.<br />
* [http://asic.ethz.ch/2015/Phoebe.html Phoebe] an improved version of [http://asic.ethz.ch/2014/Selene.html Selene], 4 cores and 1 shared vectorial FPU using logarithmic number system<br />
* [http://asic.ethz.ch/2015/Imperio.html Imperio] single core RISC-V based PULPino system. Has the PULP DNA, but is a single core microprocessor complete with peripherals from the PULP project. <br />
====130nm====<br />
* [http://asic.ethz.ch/2015/Vivosoc.html Vivosoc] 2 core mixed-signal PULP system with a low-power A/D converter (130nm)<br />
====180nm====<br />
* [http://asic.ethz.ch/2013/Or10n.html Or10n] An optimized implementation of the OpenRISC processor developed to be used within PULP.<br />
* [http://asic.ethz.ch/2013/Sir10us.html Sir10us] A cryptographic application that uses the Or10n processor developed for PULP.<br />
* [http://asic.ethz.ch/2015/Sid.html Sid] Large PULP chip with in-exact accelerators, LL version<br />
* [http://asic.ethz.ch/2015/Diego.html Diego] Large PULP chip with in-exact accelerators, LVT version <br />
* [http://asic.ethz.ch/2015/Manny.html Manny] Large PULP chip with in-exact accelerators, sub-threshold version<br />
<br />
<br />
===Publications===<br />
<br />
====2016====<br />
<br />
* ''PULPino: A small single-core RISC-V SoC'', A. Traber, F. Zaruba, S. Stucki, A. Pullini, G. Haugou, E. Flamand, F. K. Gürkaynak, L. Benini, RISC-V Workshop, 2016, [http://riscv.org/workshop-jan2016/Wed1315%20PULP%20riscv3_noanim.pdf slides], [[Media:pulpino_poster_riscv2015.pdf|poster]]<br />
<br />
* ''Enabling the Heterogeneous Accelerator Model on Ultra-Low Power Microcontroller Platforms'', F. Conti, D. Palossi, A. Marongiu, D. Rossi, L. Benini, DATE, 2016 (to appear)<br />
<br />
* ''High-Efficiency Logarithmic Number Unit Design based on an Improved Cotransformation Scheme'', Y. Popoff, F. Scheidegger, M. Schaffner, M. Gautschi, F. K. Gürkaynak, L. Benini, DATE, 2016 (to appear)<br />
<br />
* ''A 65nm CMOS 6.4-to-29.2pJ/FLOP@0.8V Shared Logarithmic Floating Point Unit for Acceleration of Nonlinear Function Kernels in a Tightly Coupled Processor Cluster'', M. Gautschi, M. Schaffner, F. K. Gürkaynak, L. Benini, ISSCC, 2016, [http://dx.doi.org/10.1109/ISSCC.2016.7417917 paper]<br />
<br />
* ''Accuracy and Performance Trade-offs of Logarithmic Number Units in Multi-Core Clusters'', M. Schaffner, M. Gautschi, F. K. Gürkaynak, L. Benini, ARITH, 2016<br />
<br />
====2015====<br />
<br />
* ''A Ultra-Low-Energy Convolution Engine for Fast Brain-inspired Vision in Multicore Clusters'', F. Conti, L. Benini, DATE, 2015, [http://dl.acm.org/citation.cfm?id=2755753.2755910 paper]<br />
<br />
* ''Lightweight virtual memory support for many-core accelerators in heterogeneous embedded SoCs'', P. Vogel, A. Marongiu, L. Benini, CODES+ISSS, 2015, [http://dx.doi.org/10.1109/CODESISSS.2015.7331367 paper]<br />
<br />
* ''PULP: OpenRISC-based ultra-low power parallel platform'', D. Rossi, F. Conti, A. Pullini, I. Loi, M. Gautschi, D. Palossi, A. Marongiu, G. Haugou, L. Benini, ORCONF, 2015, [https://www.dropbox.com/s/qs3jbqqiz0948tj/PULP_ORCONF15.pptx?dl=0 slides][https://www.youtube.com/watch?v=HX-QHTMvuzk&list=PLUg3wIOWD8yoX2ECfeU_QP5snbu2Zs1Wp&index=3 video]<br />
<br />
* ''PULPino: A RISC-V based single-core system'', A. Traber, S. Stucki, F. Zaruba, M. Gautschi, A. Pullini, I. Loi, D. Rossi, G. Haugou, F. K. Gürkaynak, L. Benini, ORCONF, 2015, [https://www.dropbox.com/s/vtrgqnc7dm7gbx2/Andreas%20Traber%20-%20pulpino.pdf?dl=0 slides][https://www.youtube.com/watch?v=-_zGoJmPddo&index=4&list=PLUg3wIOWD8yoX2ECfeU_QP5snbu2Zs1Wp video]<br />
<br />
* ''Exploring Multi-banked Shared-L1 Program Cache on Ultra-Low Power Tightly Coupled Processor Clusters'', I. Loi, D. Rossi, G. Haugou, M. Gautschi, L. Benini, ACM Computing Frontiers, 2015, [http://dx.doi.org/10.1145/2742854.2747288 paper]<br />
<br />
* ''PULP: A Ultra-Low Power Parallel Accelerator for Energy-Efficient and Flexible Embedded Vision'', F. Conti, D. Rossi, A. Pullini, I. Loi, L. Benini, Journal of Signal Processing Systems, October 2015, [http://link.springer.com/article/10.1007%2Fs11265-015-1070-9 paper]<br />
<br />
* ''A −1.8V to 0.9V body bias, 60 GOPS/W 4-core cluster in low-power 28nm UTBB FD-SOI technology'', D. Rossi, A. Pullini, M. Gautschi, I. Loi, F.K. Gurkaynak, P. Flatresse, L. Benini, S3S, October 2015, [http://dx.doi.org/10.1109/S3S.2015.7333483 paper]<br />
<br />
* ''A 60 GOPS/W, −1.8 V to 0.9 V body bias ULP cluster in 28 nm UTBB FD-SOI technology'', D. Rossi, A. Pullini, I. Loi, F. K. Gürkaynak, A. Bartolini, P. Flatresse, L. Benini, Solid-State Electronics, 2016, [http://dx.doi.org/10.1016/j.sse.2015.11.015 paper] <br />
<br />
* ''PULP: A Parallel Ultra-Low-Power Platform for Next Generation IoT Applications'', D. Rossi, F. Conti, A. Marongiu, A. Pullini, I. Loi, M. Gautschi, G. Tagliavini, A. Capotondi, P. Flatresse, L. Benini, HOT Chips, 2015, [http://www.hotchips.org/wp-content/uploads/hc_archives/hc27/HC27.24-Monday-Epub/HC27.24.10-IoT-Epub/HC27.24.111-PULP-Rossi-DEL-ETH-2.pdf slides]<br />
<br />
* ''Tailoring instruction-set extensions for an ultra-low power tightly-coupled cluster of OpenRISC cores'', M. Gautschi, A. Traber, A. Pullini, L. Benini, M. Scandale, A. Di Federico, M. Beretta, G. Agosta, VLSI-SoC, 2015, [http://dx.doi.org/10.1109/VLSI-SoC.2015.7314386 paper]<br />
<br />
<br />
====2014====<br />
<br />
* ''Energy-efficient vision on the PULP platform for ultra-low power parallel computing'', F. Conti, D. Rossi, A. Pullini, I. Loi, L. Benini, SiPS, 2014, [http://dx.doi.org/10.1109/SiPS.2014.6986099 paper]<br />
<br />
* ''Ultra-low-latency lightweight DMA for tightly coupled multi-core clusters'', D. Rossi, I. Loi, G. Haugou, L. Benini, ACM Computing Frontiers, 2014, [http://dx.doi.org/10.1145/2597917.2597922 paper]<br />
<br />
* ''Customizing an Open Source Processor to Fit in an Ultra-Low Power Cluster with a Shared L1 Memory'', M. Gautschi, D. Rossi, L. Benini, GLSVLSI, 2014, [http://dx.doi.org/10.1145/2591513.2591569 paper]<br />
<br />
* ''Energy efficient parallel computing on the PULP platform with support for OpenMP'', D. Rossi, I. Loi, F. Conti, G. Tagliavini, A. Pullini, A. Marongiu, IEEEI, 2014, [http://dx.doi.org/10.1109/EEEI.2014.7005803 paper]<br />
<br />
===Links===<br />
* [http://www.pulp-platform.org Official PULP Project Website]<br />
* [https://github.com/pulp-platform/pulpino PULPino on GitHub] <br />
* [http://iis.ee.ethz.ch/~haugoug/pulp PULP SDK] (Software Development Kit)<br />
* [http://www-micrel.deis.unibo.it/pulp-project PULP page in University of Bologna]<br />
* [http://compilergroup.elet.polimi.it/doku.php?id=research:pulp LLVM compiler for PULP developed by Politecnico di Milano] <br />
** [http://compilergroup-srv.elet.polimi.it/toolchains/or1k-toolchain-linux-amd64-latest.tar.gz Latest compiled toolchain for Linux EL6]<br />
<br />
<br />
===Templates and Logos===<br />
[[Media:pulp_logos.tar|This archive]] contains all PULP logos below as well as inverted versions thereof for dark backgrounds (in PDF and PNG formats). Also, it includes the "Orbitron" font which has been used here.<br />
<br />
For documentation, please use the following [[Media:Pulp_ug_template_v1.0.tar.gz|Word template (v1.0)]]. And here is a PULP [[Media:Pulp_slide_template_v1.0.pptx|slide template for Powerpoint (v1.0)]].<br />
<br />
====Inline====<br />
[[File:pulp_logo_inline2.png|250px|Inline PULP logo, variant 2 ([[Media:pulp_logo_inline2.png|PNG]] [[Media:pulp_logo_inline2.pdf|PDF]]).]]<br />
[[File:pulp_logo_inline1.png|250px|Inline PULP logo, variant 1 ([[Media:pulp_logo_inline1.png|PNG]] [[Media:pulp_logo_inline1.pdf|PDF]]).]]<br />
====Big====<br />
[[File:pulp_logo_big2.png|140px|Big PULP logo, variant 2 ([[Media:pulp_logo_big2.png|PNG]] [[Media:pulp_logo_big2.pdf|PDF]]).]]<br />
[[File:pulp_logo_big1.png|140px|Big PULP logo, variant 1 ([[Media:pulp_logo_big1.png|PNG]] [[Media:pulp_logo_big1.pdf|PDF]]).]]<br />
[[File:pulp_logo_icon.png|140px|Main PULP logo icon ([[Media:pulp_logo_icon.png|PNG]] [[Media:pulp_logo_icon.pdf|PDF]]).]] <br />
<br />
[[Category:PULP]]</div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=Completed&diff=2149Completed2016-04-14T17:41:29Z<p>Schaffner: </p>
<hr />
<div>These projects have already been completed. You can take a look at the results of the project and learn more.<br />
<br />
==Analog==<br />
===2016===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Completed<br />
category = Analog<br />
category = 2016<br />
</DynamicPageList><br />
===2015===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Completed<br />
category = Analog<br />
category = 2015<br />
</DynamicPageList><br />
===2014===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Completed<br />
category = Analog<br />
category = 2014<br />
</DynamicPageList><br />
===2013===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Completed<br />
category = Analog<br />
category = 2013<br />
</DynamicPageList><br />
===2012===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Completed<br />
category = Analog<br />
category = 2012<br />
</DynamicPageList><br />
<br />
==Digital==<br />
===2016===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Completed<br />
category = Digital<br />
category = 2016<br />
</DynamicPageList><br />
===2015===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Completed<br />
category = Digital<br />
category = 2015<br />
</DynamicPageList><br />
===2014===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Completed<br />
category = Digital<br />
category = 2014<br />
</DynamicPageList><br />
===2013===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Completed<br />
category = Digital<br />
category = 2013<br />
</DynamicPageList><br />
===2012===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Completed<br />
category = Digital<br />
category = 2012<br />
</DynamicPageList><br />
<br />
==Nano Electronics==<br />
===2016===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Completed<br />
category = Nano Electronics<br />
category = 2016<br />
</DynamicPageList><br />
===2015===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Completed<br />
category = Nano Electronics<br />
category = 2015<br />
</DynamicPageList><br />
===2014===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Completed<br />
category = Nano Electronics<br />
category = 2014<br />
</DynamicPageList><br />
===2013===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Completed<br />
category = Nano Electronics<br />
category = 2013<br />
</DynamicPageList><br />
===2012===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Completed<br />
category = Nano Electronics<br />
category = 2012<br />
</DynamicPageList><br />
<br />
==Nano TCAD==<br />
===2016===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Completed<br />
category = Nano-TCAD<br />
category = 2016<br />
</DynamicPageList><br />
===2015===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Completed<br />
category = Nano-TCAD<br />
category = 2015<br />
</DynamicPageList><br />
===2014===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Completed<br />
category = Nano-TCAD<br />
category = 2014<br />
</DynamicPageList><br />
===2013===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Completed<br />
category = Nano-TCAD<br />
category = 2013<br />
</DynamicPageList><br />
===2012===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Completed<br />
category = Nano-TCAD<br />
category = 2012<br />
</DynamicPageList></div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=Spatio-Temporal_Video_Filtering&diff=2148Spatio-Temporal Video Filtering2016-04-14T17:40:36Z<p>Schaffner: </p>
<hr />
<div>[[File:spt_filtering.jpg|thumb|400px|Spatio temporal filtering example where sparse flow vectors are converted to a dense flow-field ([http://www.disneyresearch.com/wp-content/uploads/Practical-Temporal-Consistency-for-Image-Based-Graphics-Applications-Paper.pdf from]).]]<br />
==Short Description==<br />
There are many image and video processing algorithms (e.g. calculation of Optical-Flow, or Image Domain Warps) that are usually solved using large optimization problems. The solution of such <br />
large optimization problems in real-time is difficult and sometimes even infeasible. However the mathematical structure of some of these problems allows us to approximate their solution by using<br />
non-linear filtering in the spatial and temporal domain. These filters scale better in terms of computational complexity than the corresponding optimization problems, and therefore would <br />
allow to perform certain video processing steps more efficiently. In this project we would like to evaluate different filtering kernels with respect to hardware efficiency, and develop an efficient<br />
hardware architecture which is capable of filtering a high definition video stream in real time.<br />
<br />
The project is quite open at the moment and is suitable for Master and Semester Theses.<br />
<br />
<br />
===Status: Available ===<br />
: Scope: Semester or Master Thesis<br />
: Looking for 1-2 Interested Students<br />
: Supervisors: [[:User:schaffner|Michael Schaffner]], [[:User:Lukasc|Lukas Cavigelli]]<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: Introductory course in computer vision (optional)<br />
: Interest in computer graphics / computer vision<br />
: Matlab, VHDL and C++<br />
<br />
===Character===<br />
<br />
TBD<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang] ---><br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
===Partners===<br />
: [http://www.disneyresearch.com/research-labs/disney-research-zurich Disney Research Zurich]<br />
<br />
[[#top|↑ top]]<br />
<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
----<br />
<br />
[[#top|↑ top]]<br />
[[Category:Image and Video Processing]] [[Category:Digital]] [[Category:Research]] [[Category:Master Thesis]] [[Category:Semester Thesis]] [[Category:Hot]] [[Category:Completed]][[Category:ASIC]] [[Category:FPGA]] [[Category:2016]]</div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=Digital&diff=2147Digital2016-04-14T17:40:03Z<p>Schaffner: /* Completed Projects */</p>
<hr />
<div>Projects that are part of the Digital Circuits and Systems group<br />
<br />
==Available Projects==<br />
We are still looking for students/partners to work on the following projects<br />
<br />
<br />
===HOT Topics===<br />
<DynamicPageList><br />
category = Available<br />
category = Digital<br />
category = Hot<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
===ASIC Design===<br />
<DynamicPageList><br />
category = Available<br />
category = Digital<br />
category = ASIC<br />
suppresserrors=true<br />
</DynamicPageList><br />
===FPGA Design===<br />
<DynamicPageList><br />
category = Available<br />
category = Digital<br />
suppresserrors=true<br />
category = FPGA<br />
</DynamicPageList><br />
===System Design===<br />
<DynamicPageList><br />
category = Available<br />
category = Digital<br />
suppresserrors=true<br />
category = System Design <br />
</DynamicPageList><br />
===System Software Development===<br />
<DynamicPageList><br />
category = Available<br />
category = Digital<br />
category = Software<br />
suppresserrors=true<br />
</DynamicPageList><br />
===Processor Design===<br />
<DynamicPageList><br />
category = Available<br />
category = Digital<br />
suppresserrors=true<br />
category = Processor<br />
</DynamicPageList><br />
===Cryptography===<br />
<DynamicPageList><br />
category = Available<br />
category = Digital<br />
suppresserrors=true<br />
category = Cryptography<br />
</DynamicPageList><br />
===Telecommunication Circuits===<br />
<DynamicPageList><br />
category = Available<br />
category = Digital<br />
suppresserrors=true<br />
category = Telecommunications<br />
</DynamicPageList><br />
===Others===<br />
<DynamicPageList><br />
suppresserrors=true<br />
notcategory = ASIC<br />
notcategory = FPGA<br />
notcategory = System Design <br />
notcategory = Telecommunications<br />
notcategory = Cryptography<br />
notcategory = Processor<br />
category = Available<br />
category = Digital<br />
</DynamicPageList><br />
<br />
==Active Projects==<br />
These are the projects that are currently active<br />
<DynamicPageList><br />
category = In progress<br />
category = Digital<br />
</DynamicPageList><br />
<br />
==Completed Projects==<br />
These are projects that were completed in the last few years<br />
===2016===<br />
<DynamicPageList><br />
category = Completed<br />
category = Digital<br />
category = 2016<br />
suppresserrors=true<br />
</DynamicPageList><br />
===2015===<br />
<DynamicPageList><br />
category = Completed<br />
category = Digital<br />
category = 2015<br />
suppresserrors=true<br />
</DynamicPageList><br />
===2014===<br />
<DynamicPageList><br />
category = Completed<br />
category = Digital<br />
category = 2014<br />
</DynamicPageList><br />
===2013===<br />
<DynamicPageList><br />
category = Completed<br />
category = Digital<br />
category = 2013<br />
</DynamicPageList><br />
===2012===<br />
<DynamicPageList><br />
category = Completed<br />
category = Digital<br />
category = 2012<br />
</DynamicPageList><br />
===2011===<br />
<DynamicPageList><br />
category = Completed<br />
category = Digital<br />
category = 2011<br />
</DynamicPageList></div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=Research&diff=2146Research2016-04-14T17:38:41Z<p>Schaffner: </p>
<hr />
<div>Research projects at the Integrated Systems Laboratory (IIS).<br />
==2016==<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = 2016<br />
category = Research<br />
</DynamicPageList><br />
==2015==<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = 2015<br />
category = Research<br />
</DynamicPageList><br />
==2014==<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = 2014<br />
category = Research<br />
</DynamicPageList><br />
==2013==<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = 2013<br />
category = Research<br />
</DynamicPageList><br />
==2012==<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = 2012<br />
category = Research<br />
</DynamicPageList><br />
==2011==<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = 2011<br />
category = Research<br />
</DynamicPageList><br />
==2010==<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = 2010<br />
category = Research<br />
</DynamicPageList></div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=DMA_Streaming_Co-processor&diff=2145DMA Streaming Co-processor2016-04-14T17:36:20Z<p>Schaffner: </p>
<hr />
<div>==Short Description==<br />
[[File:Ap signals.png|400px|thumb|right|Sample Preprocessing]]<br />
[[File:StreamingProc.png|thumb|400px|The streaming processor would act as a co-processor for the DMA in the PULP cluster.]]<br />
In many cases a lot of resources are consumed during a preprocessing phase in which the raw data coming, e.g., from an image sensor is transformed in a proper way before being fed to the main processing algorithms. This preprocessing, in many cases, could be done very efficiently while moving the data through the memory hierarchy (e.g. L2 -> L1 transfers).<br />
<br />
Like other processors, the PULP platform provides a standard DMA controller for efficient data transfers. In this work, we are going to design a streaming co-processor for the DMA with limited programmability. <br />
This co-processor could then perform such tasks on-the-fly when the data is being copied.<br />
<br />
Potential application candidates include signal filtering for audio/motion sensor, sub/over sampling, color scheme conversion, image filtering, ciphering and compression/decompression. <br />
<br />
===Status: Available ===<br />
: Scope: Semester or Master Thesis<br />
: Looking for 1-2 Interested Students<br />
: Supervisors: [[:User:schaffner|Michael Schaffner]], [[:User:gautschi|Michael Gautschi]], [[:User:Pullinia|Antonio Pullini]]<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: Basic Computer Architecture Course<br />
: Matlab, VHDL and C++<br />
<br />
===Character===<br />
: 20% Theory & Literature Study<br />
: 30% Evaluations<br />
: 50% Hw Architecture & ASIC Implementation<br />
<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang] ---><br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
[[#top|↑ top]]<br />
<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
----<br />
<br />
[[#top|↑ top]]<br />
[[Category:Digital]] [[Category:Master Thesis]] [[Category:Semester Thesis]] [[Category:Available]] [[Category:ASIC]] [[Category:UlpSoC]] [[Category:PULP]] [[Category:Processor]] [[Category:2016]]</div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=Design_of_a_Fused_Multiply_Add_Floating_Point_Unit&diff=2144Design of a Fused Multiply Add Floating Point Unit2016-04-14T17:34:15Z<p>Schaffner: </p>
<hr />
<div>[[File:fpu_fma.png|400px|right|thumb]]<br />
==Short Description==<br />
''Floating point units'' (FPU) are one part of a micro-processor and usually directly integrated in the pipeline. In a multi-processor environment one private FPU per processor core is not the most energy efficient implementation because ''floating point'' (FP)-operations are not always used which means they remain idle for lots of cycles. Sharing FPUs among the processors is expected to improve the utilization of the FPUs and therefore reduce the overall power consumption of the system. We have already designed a FPU unit with support for FP-additions, FP-subtractions, and FP-Multiplications and shared in a multi-core cluster ''PULP''. Since it is a simple architecture, it consumes only little area and gives only little area savings when it is shared in a cluster.<br />
<br />
In linear algebra we often face multiply-add operations which could be very efficiently handled by an FPU which is capable of doing multiply-add in a fused unit.<br />
<br />
Your task will be to come up with an hardware efficient architecture for a fused multiply-add FPU, implement it in System Verilog and plug it to the RISC-V processor.<br />
<br />
===Status: Available ===<br />
: Supervisors: [[:User:gautschi|Michael Gautschi]], [[:User:schaffner|Michael Schaffner]]<br />
<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: Interest in Computer Architectures<br />
: System Verilog knowledge<br />
<br />
===Character===<br />
: 25% Theory<br />
: 50% ASIC Design<br />
: 25% Verification<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang] ---><br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
[[#top|↑ top]]<br />
<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
<br />
[[Category:Digital]] [[Category:Semester Thesis]] [[Category:Available]] [[Category:UlpSoC]] [[Category:2016]] [[Category:ASIC]] [[Category:PULP]]</div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=DMA_Streaming_Co-processor&diff=2143DMA Streaming Co-processor2016-04-14T17:32:15Z<p>Schaffner: </p>
<hr />
<div>==Short Description==<br />
[[File:Ap signals.png|400px|thumb|right|Sample Preprocessing]]<br />
[[File:StreamingProc.png|thumb|400px|The streaming processor would act as a co-processor for the DMA in the PULP cluster.]]<br />
In many cases a lot of resources are consumed during a preprocessing phase in which the raw data coming, e.g., from an image sensor is transformed in a proper way before being fed to the main processing algorithms. This preprocessing, in many cases, could be done very efficiently while moving the data through the memory hierarchy (e.g. L2 -> L1 transfers).<br />
<br />
Like other processors, the PULP platform provides a standard DMA controller for efficient data transfers. In this work, we are going to design a streaming co-processor for the DMA with limited programmability. <br />
This co-processor could then perform such tasks on-the-fly when the data is being copied.<br />
<br />
Potential application candidates include signal filtering for audio/motion sensor, sub/over sampling, color scheme conversion, image filtering, ciphering and compression/decompression. <br />
<br />
===Status: Available ===<br />
: Scope: Semester or Master Thesis<br />
: Looking for 1-2 Interested Students<br />
: Supervisors: [[:User:schaffner|Michael Schaffner]], [[:User:gautschi|Michael Gautschi]], [[:User:Pullinia|Antonio Pullini]]<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: Basic Computer Architecture Course<br />
: Matlab, VHDL and C++<br />
<br />
===Character===<br />
: 20% Theory & Literature Study<br />
: 30% Evaluations<br />
: 50% Hw Architecture & ASIC Implementation<br />
<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang] ---><br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
[[#top|↑ top]]<br />
<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
----<br />
<br />
[[#top|↑ top]]<br />
[[Category:Digital]] [[Category:Master Thesis]] [[Category:Semester Thesis]] [[Category:Available]] [[Category:ASIC]] [[Category:UlpSoC]] [[Category:PULP]] [[Category:2016]]</div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=Audio_Video_Preprocessing_In_Parallel_Ultra_Low_Power_Platform&diff=2142Audio Video Preprocessing In Parallel Ultra Low Power Platform2016-04-14T17:31:11Z<p>Schaffner: </p>
<hr />
<div>==Short Description==<br />
[[File:Ap signals.png|400px|thumb|right|Sample Preprocessing]]<br />
[[File:Ap preprocIP.png|400px|thumb|right|Architectural Diagram with Preprocessing IP]]<br />
Audio and video processing on embedded systems has many constraints coming from the fewer available resources. In many cases a lot of resources are consumed during a preprocessing phase in which the raw data coming from the sensor is transformed in a proper way before being fed to the main processing algorithms. This preprocessing, in many cases,could be done very efficiently in hw reducing significantly the load on the CPU. Potential candidates include signal filtering for audio/motion sensor, sub/over sampling, color scheme conversion, image filtering, ciphering and compression/decompression. The HW IP will need to be as much as possible usable with different processing algorithms to maintain as much as possible the general purpose philosophy of the whole system.<br />
<br />
The goal of this project is to evaluate the best trade off between HW and SW in the preprocessing step for few A/V processing algorithms<br />
<br />
===Status: Available ===<br />
: Semester/Master Thesis<br />
: Supervision: [[:User:Pullinia|Antonio Pullini (IIS)]]<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<br />
===Character===<br />
: 60% Theory, Algorithms and Simulation<br />
: 40% HW Design<br />
<br />
===Requirements===<br />
: Matlab<br />
: Good C programming skills<br />
: Knowledge of digital circuit design<br />
: Knowledge of at least one HDL(VHDL, Verilog, SystemVerilog)<br />
<br />
==Links== <br />
<br />
[[#top|↑ top]]<br />
<br />
[[Category:Digital]]<br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:ASIC]] [[Category:UlpSoC]] [[Category:PULP]] [[Category:2016]]</div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=Fast_Wakeup_From_Deep_Sleep_State&diff=2141Fast Wakeup From Deep Sleep State2016-04-14T17:31:00Z<p>Schaffner: </p>
<hr />
<div>==Short Description==<br />
[[File:Ap iot pattern.png|400px|thumb|right|Typical IoT power cycle]]<br />
[[File:Ap fulmine arch.png|400px|thumb|right|Architecture with reusable IPs highlighted]]<br />
Ultra-low power operation and extreme energy efficiency are strong requirements for a number of high-growth application areas, such as E-health, Internet of Things, and wearable Human-Computer Interfaces.<br />
Most of the applications do not need an always-on system and often implement aggressive duty cycling to minimize the average power consumption. In such applications optimizing the wakeup energy consumption has a significant impact on the overall energy drawn from the battery.<br />
The goal of the project is to implement an hardware IP to enable fast save and restore of the status of the PULP multicore platform reusing as much as possible existing components.<br />
The project can be summarized as follows:<br />
*Implement SW based save/restore<br />
*Extend the current debug unit and make it memory mapped<br />
*Control system DMA to save/restore L1 data memory<br />
*Dump core state to memory via debug unit<br />
*Validate the design and compare with SW solution<br />
*Power estimation<br />
<br />
===Status: Available ===<br />
: Semester/Master Thesis<br />
: Supervision: [[:User:Pullinia|Antonio Pullini (IIS)]]<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<br />
===Character===<br />
: 20% Embedded programming<br />
: 40% HW design<br />
: 40% System validation<br />
<br />
===Requirements===<br />
Knowledge of C/C++<br />
VHDL or Verilog HDL<br />
<br />
==Links== <br />
<br />
[[#top|↑ top]]<br />
<br />
[[Category:Digital]]<br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:ASIC]] [[Category:UlpSoC]] [[Category:PULP]] [[Category:2016]]</div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=Fast_Wakeup_From_Deep_Sleep_State&diff=2140Fast Wakeup From Deep Sleep State2016-04-14T17:30:13Z<p>Schaffner: </p>
<hr />
<div>==Short Description==<br />
[[File:Ap iot pattern.png|400px|thumb|right|Typical IoT power cycle]]<br />
[[File:Ap fulmine arch.png|400px|thumb|right|Architecture with reusable IPs highlighted]]<br />
Ultra-low power operation and extreme energy efficiency are strong requirements for a number of high-growth application areas, such as E-health, Internet of Things, and wearable Human-Computer Interfaces.<br />
Most of the applications do not need an always-on system and often implement aggressive duty cycling to minimize the average power consumption. In such applications optimizing the wakeup energy consumption has a significant impact on the overall energy drawn from the battery.<br />
The goal of the project is to implement an hardware IP to enable fast save and restore of the status of the PULP multicore platform reusing as much as possible existing components.<br />
The project can be summarized as follows:<br />
*Implement SW based save/restore<br />
*Extend the current debug unit and make it memory mapped<br />
*Control system DMA to save/restore L1 data memory<br />
*Dump core state to memory via debug unit<br />
*Validate the design and compare with SW solution<br />
*Power estimation<br />
<br />
===Status: Available ===<br />
: Semester/Master Thesis<br />
: Supervision: [[:User:Pullinia|Antonio Pullini (IIS)]]<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<br />
===Character===<br />
: 20% Embedded programming<br />
: 40% HW design<br />
: 40% System validation<br />
<br />
===Requirements===<br />
Knowledge of C/C++<br />
VHDL or Verilog HDL<br />
<br />
==Links== <br />
<br />
[[#top|↑ top]]<br />
<br />
[[Category:Digital]]<br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]</div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=Audio_Video_Preprocessing_In_Parallel_Ultra_Low_Power_Platform&diff=2139Audio Video Preprocessing In Parallel Ultra Low Power Platform2016-04-14T17:29:53Z<p>Schaffner: </p>
<hr />
<div>==Short Description==<br />
[[File:Ap signals.png|400px|thumb|right|Sample Preprocessing]]<br />
[[File:Ap preprocIP.png|400px|thumb|right|Architectural Diagram with Preprocessing IP]]<br />
Audio and video processing on embedded systems has many constraints coming from the fewer available resources. In many cases a lot of resources are consumed during a preprocessing phase in which the raw data coming from the sensor is transformed in a proper way before being fed to the main processing algorithms. This preprocessing, in many cases,could be done very efficiently in hw reducing significantly the load on the CPU. Potential candidates include signal filtering for audio/motion sensor, sub/over sampling, color scheme conversion, image filtering, ciphering and compression/decompression. The HW IP will need to be as much as possible usable with different processing algorithms to maintain as much as possible the general purpose philosophy of the whole system.<br />
<br />
The goal of this project is to evaluate the best trade off between HW and SW in the preprocessing step for few A/V processing algorithms<br />
<br />
===Status: Available ===<br />
: Semester/Master Thesis<br />
: Supervision: [[:User:Pullinia|Antonio Pullini (IIS)]]<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<br />
===Character===<br />
: 60% Theory, Algorithms and Simulation<br />
: 40% HW Design<br />
<br />
===Requirements===<br />
: Matlab<br />
: Good C programming skills<br />
: Knowledge of digital circuit design<br />
: Knowledge of at least one HDL(VHDL, Verilog, SystemVerilog)<br />
<br />
==Links== <br />
<br />
[[#top|↑ top]]<br />
<br />
[[Category:Digital]]<br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]</div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=DMA_Streaming_Co-processor&diff=2138DMA Streaming Co-processor2016-04-14T17:28:24Z<p>Schaffner: </p>
<hr />
<div>==Short Description==<br />
[[File:Ap signals.png|400px|thumb|right|Sample Preprocessing]]<br />
[[File:StreamingProc.png|thumb|400px|The streaming processor would act as a co-processor for the DMA in the PULP cluster.]]<br />
In many cases a lot of resources are consumed during a preprocessing phase in which the raw data coming, e.g., from an image sensor is transformed in a proper way before being fed to the main processing algorithms. This preprocessing, in many cases, could be done very efficiently while moving the data through the memory hierarchy (e.g. L2 -> L1 transfers).<br />
<br />
Like other processors, the PULP platform provides a standard DMA controller for efficient data transfers. In this work, we are going to design a streaming co-processor for the DMA with limited programmability. <br />
This co-processor could then perform such tasks on-the-fly when the data is being copied.<br />
<br />
Potential application candidates include signal filtering for audio/motion sensor, sub/over sampling, color scheme conversion, image filtering, ciphering and compression/decompression. <br />
<br />
===Status: Available ===<br />
: Scope: Semester or Master Thesis<br />
: Looking for 1-2 Interested Students<br />
: Supervisors: [[:User:schaffner|Michael Schaffner]], [[:User:gautschi|Michael Gautschi]], [[:User:Pullinia|Antonio Pullini]]<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: Basic Computer Architecture Course<br />
: Matlab, VHDL and C++<br />
<br />
===Character===<br />
: 10% Theory & Literature Study<br />
: 20% Evaluations<br />
: 70% Hw Architecture & ASIC Implementation<br />
<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang] ---><br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
[[#top|↑ top]]<br />
<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
----<br />
<br />
[[#top|↑ top]]<br />
[[Category:Digital]] [[Category:Master Thesis]] [[Category:Semester Thesis]] [[Category:Available]] [[Category:ASIC]] [[Category:UlpSoC]] [[Category:PULP]] [[Category:2016]]</div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=DMA_Streaming_Co-processor&diff=2137DMA Streaming Co-processor2016-04-14T17:28:02Z<p>Schaffner: </p>
<hr />
<div>==Short Description==<br />
[[File:Ap signals.png|400px|thumb|right|Sample Preprocessing]]<br />
[[File:StreamingProc.png|thumb|400px|The streaming processor would act as a co-processor for the DMA in the PULP cluster.]]<br />
In many cases a lot of resources are consumed during a preprocessing phase in which the raw data coming, e.g., from an image sensor is transformed in a proper way before being fed to the main processing algorithms. This preprocessing, in many cases, could be done very efficiently while moving the data through the memory hierarchy (e.g. L2 -> L1 transfers).<br />
<br />
Like other processors, the PULP platform provides a standard DMA controller for efficient data transfers. In this work, we are going to design a streaming co-processor for the DMA with limited programmability. <br />
This co-processor could then perform such tasks on-the-fly when the data is being copied.<br />
<br />
Potential application candidates include signal filtering for audio/motion sensor, sub/over sampling, color scheme conversion, image filtering, ciphering and compression/decompression. <br />
<br />
===Status: Available ===<br />
: Scope: Semester or Master Thesis<br />
: Looking for 1-2 Interested Students<br />
: Supervisors: [[:User:schaffner|Michael Schaffner]], [[:User:gautschi|Michael Gautschi]], [[:User:Pullinia|Antonio Pullini]]<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: Basic Computer Architecture Course<br />
: Matlab, VHDL and C++<br />
<br />
===Character===<br />
: 10% Theory & Literature Study<br />
: 20% Evaluations<br />
: 70% Hw Architecture & ASIC Implementation<br />
<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang] ---><br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
===Partners===<br />
<br />
[[#top|↑ top]]<br />
<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
----<br />
<br />
[[#top|↑ top]]<br />
[[Category:Digital]] [[Category:Master Thesis]] [[Category:Semester Thesis]] [[Category:Available]] [[Category:ASIC]] [[Category:UlpSoC]] [[Category:PULP]] [[Category:2016]]</div>Schaffnerhttp://iis-projects.ee.ethz.ch/index.php?title=DMA_Streaming_Co-processor&diff=2136DMA Streaming Co-processor2016-04-14T17:26:59Z<p>Schaffner: </p>
<hr />
<div>[[File:StreamingProc.png|thumb|400px|The streaming processor would act as a co-processor for the DMA in the PULP cluster.]]<br />
==Short Description==<br />
<br />
In many cases a lot of resources are consumed during a preprocessing phase in which the raw data coming, e.g., from an image sensor is transformed in a proper way before being fed to the main processing algorithms. This preprocessing, in many cases, could be done very efficiently while moving the data through the memory hierarchy (e.g. L2 -> L1 transfers).<br />
<br />
Like other processors, the PULP platform provides a standard DMA controller for efficient data transfers. In this work, we are going to design a streaming co-processor for the DMA with limited programmability. <br />
This co-processor could then perform such tasks on-the-fly when the data is being copied.<br />
<br />
Potential application candidates include signal filtering for audio/motion sensor, sub/over sampling, color scheme conversion, image filtering, ciphering and compression/decompression. <br />
<br />
===Status: Available ===<br />
: Scope: Semester or Master Thesis<br />
: Looking for 1-2 Interested Students<br />
: Supervisors: [[:User:schaffner|Michael Schaffner]], [[:User:gautschi|Michael Gautschi]], [[:User:Pullinia|Antonio Pullini]]<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: Basic Computer Architecture Course<br />
: Matlab, VHDL and C++<br />
<br />
===Character===<br />
: 10% Theory & Literature Study<br />
: 20% Evaluations<br />
: 70% Hw Architecture & ASIC Implementation<br />
<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang] ---><br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
===Partners===<br />
<br />
[[#top|↑ top]]<br />
<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
----<br />
<br />
[[#top|↑ top]]<br />
[[Category:Digital]] [[Category:Master Thesis]] [[Category:Semester Thesis]] [[Category:Available]] [[Category:ASIC]] [[Category:UlpSoC]] [[Category:PULP]] [[Category:2016]]</div>Schaffner