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Heterogeneous Acceleration Systems

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The hardware and software stack of our Heterogeneous Embedded Research Platform (HERO).
Uniting many ICs in a single one: Heterogeneous integration has allowed (not only) Apple to get high computing performance under tight power constraints.

Your mobile phone has one [1] [2], your ultrabook has one [3], and they may soon diffuse into data centers as well [4]: Heterogeneous systems on chip are currently one of the main drivers for performance-per-energy advancements in various application domains. At their heart, these architectures combine general-purpose computing with domain-specific processing capabilities.

While this approach has the potential to bring unprecedented computing possibilities to various application domains, fundamental problems have to be solved to make heterogeneous SoCs truly ubiquitous. Most importantly, designing and programming heterogeneous SoCs to exploit their theoretical potential is challenging due to the high overall system complexity.

To be able to investigate these problems, we have built the Heterogeneous Embedded Research Platform (HERO). HERO combines an ARM Cortex-A host processor with a scalable, configurable, and extensible FPGA implementation of a programmable manycore accelerator (also developed in our group as part of the PULP project). Along its unique hardware combination, HERO features a heterogeneous software stack that supports OpenMP 4.5 and Shared Virtual Memory (SVM) for transparent accelerator programming.

In the context of this research platform, we offer projects across the entire hardware/software stack. This is your chance to explore and work on (almost) any layer of a running computer system and contribute to energy-efficient next-generation computing platforms! We are currently looking for students to work on the projects below, but are also open to discuss suggestions from you. Please contact us if you are interested!

Contact Information

Andreas Kurth

Available Projects


Projects In Progress


Completed Projects