Adapting a consistent naming scheme is one of the most important steps in order to make your code easy to understand. If signals, processes, and entities are always named the same way, any inconsistency can be detected easier. Moreover, if a design group shares the same naming convention, all members would immediately feel at home with each others code.
The Naming conventions of Microelectronics Design Center can be accessed within the ETH Zurich network on the EDA Wiki website.
The preferred editor for writing HDL, either VHDL or System Verilog code, is the emacs editor, as it has a really advanced VHDL and System Verilog mode. Because of this, you should get comfortable with the idea of using emacs, even if you like a different editor.