Design of Charge-Pump PLL in 28nm for 5G communication applications
The demand for higher speed in mobile broadband communication drives the research community to seek for new wireless spectrum to support larger capacity beyond 4G standards. Due to congested spectrum below 6 GHz, research works into higher frequency bands are explored in recent years as a hot emerging topic for both academia as well as industry. Among the frequency bands of interests, X-band as well as Ka-band are highly potentially the candidate for 5G standards, which means the high purity frequency carriers are required to be synthesized in the range from 15 GHz to even 60 GHz.
As the key for wireless transceiver system, Phase-locked loop (PLL) is a general solution for frequency synthesize. In terms of trade-off between power and noise, the design of charge pump, loop filter as well as multi-modulus divider are the key parts determining in-band performance for an analog intensive PLL. As shown in the figure above, there are quite many smart architectures introduced in recent years, such as injection-locking (ILPLL) and subsampling (SSPLL). Although these blocks are still mostly clocked at reference rate (normally 26 MHz to 64 MHz), as the wavelength comes to mm range, completely different design considerations must be taken especially with the ultra-high frequency divider design.
Therefore, the motivation of this project is to fully leverage the benefit from advanced 28nm process to push the power- performance trade-off of charge-pump PLL at mmWave frequency bands further to be competitive with state-of-art designs.
- 20% Theory
- 80% Circuit Design
Detailed Task Description
- X. Gao, E. Klumperink and B. Nauta, "Sub-sampling PLL techniques," Custom Integrated Circuits Conference (CICC), 2015 IEEE, San Jose, CA, 2015, pp. 1-8.
doi: 10.1109/CICC.2015.7338420↑ top