Design of Scalable Event-driven Neural-Recording Digital Interface
Brain Computer Interfaces (BCI) are devices that decode the brain activity and use the decoded information for a wide application range: to control games in the entertainment field, to predict epileptic seizures or in more to control the seizures, to simply record data for scientific studies. The brain activity can be extracted invasively or not. Invasive methods can be used to sense: the extracellular single neuron activity (action potentials or spikes) with very tiny electrodes close to the neuron; an average communication among neurons close to the electrode via neuron’s axons via local field potentials – LFPs. Finally, ECoG is the signal used to acquire even more neurons ‘activity more superficially, but still implanted under the skull. Non-invasive methods are also possible by sensing EEG signals with electrodes very far from the neurons. Such electrodes are placed on the scalp and acquire the macro-scale activity of the brain at very low frequency (< 40Hz).
Many-channels recording systems are made of an analog-front-end (AFE) that is composed by amplifiers, filters and analog-to-digital converters (ADCs) and a digital part that streams the signals to a digital processor. This part is usually implemented with standard protocols like SPI or USB. As most of the power is spent in transmitting, smart recording systems can be equipped of circuitry to extract and send only “interesting” portion of the signal. This reduce the bandwidth from the recording system depending on the signal activity (more interesting events --> higher bandwidth and viceversa). For instance, an epileptic seizure detection device may send to a computer only portion of the signal that contains the actual seizure and do not send anything when the brain acts normally. In the context of action potentials, a neural recording system can send to a digital processor only the spikes and do not send anything when the only content of the signal is background noise. Once a spike has been extracted, it has to be assigned to one of the neuron sensed by the electrode (one electrode can sense 1 – 4 neurons in the neighbourhood). Spikes generated by different neurons are usually different in terms of shape and amplitude. This procedure is called “Spike sorting” and can be implemented in different ways. For instance, every extracted spike can be compared against 1 to 4 templates representative of the neuron activity.
Depending on the context, neural recording systems may have from 8 - 16 channels for simple experiments with rats to 100,000 channels to study more complex neural networks as the human brain! For every application, the analog and digital part have to be re-designed, verified, tested and validated, making the process long and expensive. An extendible, systolic system composed of a network of simpler few-channels recording system would reduce the design time and simplify the other phases as the main effort in focused on the kernel device.
The goal of this thesis is to design the digital part of a neural-recording kernel device. Such device has to be parametric and programmable. It will acquire few channels (8 to 32), stream the raw data or detected packets to an SPI slave interface and it will be extended with a chip-to-chip protocol to implement a mono-directional open-ring network of kernel devices. The open-ring network is a topology where one device can only send to data to another device. Only the root sends finally the data to a computer with SPI. An analysis of the network is required to understand the bandwidth limitation. Every device can be programmed to act as the root of the network or another node. The digital interface must be programmable to set the sampling frequency, the output mode (events or raw-data streams), the node function in the network (root or intermediate node), as well as to load templates to perform the spike detection.
In the first figure, an example of the system to be realized is shown. The analog input will be only simulated in the test bench. The second figure shows the network of chips and the bandwidth among nodes.
This thesis is part of project in collaboration with the Neural Interfaces group at Imperial College London http://www.imperial.ac.uk/neural-interfaces.
The student is required to:
- Design a time-division-multiplexer acquisition unit that acquires data from the CH – channels (CH parameter 8, 16 or 32) analog front end and store them to the SRAM. Signals are acquired with a programmed sample frequency (max 30 KHz).
- Design a Digital Signal Processor to perform Template Matching (in case programmed to send only events) on a window of N samples (N parametric) for every channel and store the positive results in a buffer.
- Design an SPI slave interface as well as an event-based protocol to exchange data with an external computer.
- Design an asynchronous chip-to-chip protocol for network communication. Such communication happens from one node to another to exchange data until the root is reached. The root will also send via SPI with the protocol designed at 3) all the data from all the node to a computer. Furthermore, the computer must be able to program all the nodes in the network by sending message only to the root. An analysis of the network is needed to understand bandwidth constraints.
- Design a test bench to verify the single device as well as the network with all the aforementioned operations. The student may also test the implementation on the FPGA, useful also for a demonstrator.
- Synthesize the design in UMC180 technology and perform power simulations.
- Compare the network with a single chip solution (e.g. a network of 4 devices with 8 channels against a single device with 32 channels).
The HDL language for the design and testbench will be SystemVerilog.
To work on this project, you will need:
- to have worked in the past with at least one RTL language (SystemVerilog or Verilog or VHDL) - having followed the VLSI1 / VLSI2 courses is recommended
- to have prior knowedge of hardware design
Other skills that you might find useful include:
- familiarity with a scripting language
- to be strongly motivated for a super-cool project
If you want to work on this project, but you think that you do not match some the required skills, we can give you some preliminary exercise to help you fill in the gap.
Meetings & Presentations
The students and advisor(s) agree on weekly meetings to discuss all relevant decisions and decide on how to proceed. Of course, additional meetings can be organized to address urgent issues.
Around the middle of the project there is a design review, where senior members of the lab review your work (bring all the relevant information, such as prelim. specifications, block diagrams, synthesis reports, testing strategy, ...) to make sure everything is on track and decide whether further support is necessary. They also make the definite decision on whether the chip is actually manufactured (no reason to worry, if the project is on track) and whether more chip area, a different package, ... is provided. For more details confer to .
At the end of the project, you have to present/defend your work during a 15 min. presentation and 5 min. of discussion as part of the IIS colloquium.