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High Throughput Turbo Decoder Design

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Chip micrograph of the LTE-Advanced turbo decoder. The overlay depicts the exact locations of the 16 parallel SISO decoders used to achieve the 1Gbps throughput.




Sandro Belfanti
Christoph Roth
Christian Benkeser


ETH Zurich




The exploding demand for data-centric applications on mobile devices has led to ever-increasing data rates in mobile communication standards. The most recent 3GPP standard evolution, LTE-Advanced (LTE-A), specifies peak data rates of up to 3Gbps by adding 8x8 MIMO and increasing the radio bandwidth to 100MHz, which is almost 10x the maximum throughput of the LTE standard currently deployed around the world. In fact, LTE-A is the first true 4G standard meeting all requirements imposed by ITU, which includes providing at least 1Gbps peak throughput. These high throughput requirements combined with the flexibility mandatory to cope with a wide range of code rates and block sizes render the turbo decoder one of the key challenges in the design of user equipment for mobile communications.

In this project architectures for high-throughput turbo decoding were investigated focusing on the latency of the individual iterations as this becomes throughput limiting factor for high degrees of parallelism. Employing the results of this analysis, an LTE-A compliant turbo decoder ASIC was manufactured in 65nm CMOS. The measurements demonstrate that it can provide a maximum throughput of 1Gbps, which is the highest throughput reported in open literature. In strong contrast to other state of-the-art implementations, our decoder has been optimized for the entire range of code rates, which enables to maintain high throughput even for highest code rates without any concessions in BER performance