Implementation of a NB-IoT Positioning System
The Internet of Things (IoT) is believed to connect tens of billion devices by the year 2020 making it one of the key drivers for the semi-conductor industry. Thereby, a major part of the IoT will consist of moving devices such as unmanned cars or drones. For these kinds of applications the knowledge of the current location is essential.
Solely relying on Global Navigation Satellite Systems (GNSS) such as GPS is insufficient: In urban areas buildings block the line-of-sight between satellite and receiver making the location estimation very inaccurate. In indoor environments satellite-based positioning completely fails. Furthermore, GNSS receivers are very power-hungry which is not suitable for most of IoT applications. The 3GPP consortium responds to this need with its upcoming LTE Release 14 which will enhance the LTE Narrowband IoT (NB-IoT) standard by positioning capabilities.
In the adapted Observed Time Difference of Arrival (OTDOA) algorithm the base stations transmit reference signals as illustrated in the figure. The User Equipment (UE) detects the time difference of arrival for pairs of base stations. With the knowledge of the base stations’ exact positions it is possible to estimate the position of the device itself.
The goal of this project is the enhancement of an existing NB-IoT-baseband implementation to support the new NB-IoT positioning capability. Your first task in this project is to upgrade the available Matlab-based LTE-simulation environment to support OTDOA including the base-station as well as the UE part of the algorithm. The next task will be the integration of the UE algorithm into the available NB-IoT-baseband implementation. This step includes a hardware-software co-design in which part of the algorithm will be mapped onto a PULPino processor while computational complex tasks are realized in dedicated hardware accelerators. Finally, the implementation shall be verified by measurements on an FPGA testbed.
- Knowledge in Matlab, C and VHDL
- 40% Theory, Algorithms, and Simulation
- 40% Hardware/Software Co-Design (Programming in HDL and C)
- 20% Realization of FPGA Testbed