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Intelligent Power Management Unit (iPMU)

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Short Description

iPMU within a Generalized System

Microcontrollers targeting Internet-of-Things applications, environmental sensor networks, biomedical implants and weareables require extremely low power consumption and heavy duty-cycling. In these scenarios, the microcontroller and the required sensor and communication peripherals are usually powered by harvesting fluctuating environmental energy sources. Due to form-factor and cost constraints, the energy can only be buffered short-time in tiny energy buffers. To operate in these conditions a sophisticated power management is required.

The goal of this Semester/Master Thesis is to develop an intelligent Power Management Unit (iPMU), which can be co-integrated into the main microcontroller. The iPMU should be able to monitor the available energy for the system and learn the energy consumption of different system tasks. Moreover, the iPMU should profile the available power input from the energy harvester. By combining all this obtained knowledge, the iPMU should schedule the system tasks in an optimal way and wakeup the main processor if required. Naturally, the iPMU should consume as little power as possible (<uW) and be able to restore its functionality from complete power loss.

First, the student will have to work out the basic architecture of the iPMU and design the interface to the microprocessor. Second, he has to implement the iPMU with a hardware description language and to optimize the power consumption of the iPMU to fit the given power budget.


Status: Available

Semester/Master Thesis
Supervision: Pascal Alexander Hager (IIS)

Professor

Luca Benini

Character

60% Theory, Algorithms and Simulation
40% VHDL

Requirements

Knowledge of matlab and/or C/C++ VHDL

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