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MmWave PLL: 100GHz PLL using reference oversampling scheme

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Introduction

Inductor-less phase locked loops (PLLs) offer many advantages over LC designs, such as smaller area, wider frequency range, and less frequency pulling. However, designing a low-noise PLL using a ring oscillator is challenging due to the high oscillator noise and the stability requirement of a PLL, which limits the maximum loop bandwidth to 1/10 of the reference frequency, making it difficult to filter out oscillator noise effectively. Furthermore, simultaneous suppression of various noise sources, such as the reference, time-to-digital converter, charge-pump, loop filter and oscillator, introduces conflicting requirements. Consequently, the oscillator noise sometimes is not filtered at the maximum bandwidth. Multiplying delay-locked loops (MDLL) and injection-locked clock multipliers (ILCM) have shown promising noise performance by increasing the loop bandwidth by up to half of the reference frequency. However, because they inject the reference directly into the oscillator, they inevitably produce large spurs at the output.

Recently, a novel scheme called reference oversampling PLL (OSPLL) is gaining much attention. It can fundamentally overcome the bandwidth constraint of a PLL. The loop bandwidth can be configured to be even higher than the reference frequency so that the ring oscillator noise is effectively suppressed without the penalty of a high reference spur. Furthermore, the in-band noise can also be reduced drastically as the effective input frequency is multiplied by a factor of N, where N is the PLL frequency multiplication ratio.

Project Description

The goal of this project is to have deep understanding of reference oversampling scheme used in PLL and implement this idea into the design of 100GHz PLL.

Status: Available

Semester or master project by 1 or 2 master students
Contact: Prof. Taekwang Jang <tjang@ethz.ch>

Prerequisites

  • Analog circuit design
  • RF circuit design

Character

  • 20% Theory
  • 30% Simulation
  • 50% Circuit design

Professor

Taekwang Jang

Reference

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