Multi issue OoO Ariane Backend (M)
Ariane/CVA6 (it transitioned to Openhardware in June and was renamed to CVA6, however, we like the name and keep it as an internal code name) is a popular, 6-stage, in-order, RISC-V CPU designed as part of the PULP project and capable of booting Linux. The current Ariane backend  is built around a scoreboard (essentially a small ROB) which took over more and more functionality.
A widely employed technique to increase sequential performance (IPC) is to issue multiple instructions per cycle, we call such architectures superscalar. A second performance improvement can come from the fact that not all instructions depend on each other. Clever architecture can issue independent instructions out of program order, exploiting instruction-level parallelism (ILP).
But increasing the issue width would mean adding further ports into the scoreboard, increasing complexity, power, and reducing operating frequency.
This project proposes to re-architect the backend of Ariane (keeping the frontend and caches as well as suitable sub-blocks such as TLBs, FPU, etc.) in a similar manner as other OoO architectures such as the MIPS R10000 , Alpha 21264 , OpenPower A20 , Boom . Ideally, we would make the core parametric over the issue width (ranging from single issue up to four or six-way superscalar). The final goal is to have a reasonably advanced superscalar core running at around 1.5GHz operating frequency in a modern 12nm process with IPCs expected from that class of processor .
Depending on the timeframe further features can be added:
- RoCC Interface
- Bitmanipulation ALU
- Multi-level TLBs
- Page walk cache
- Speculative load/store disambiguation predictor 
This is an ambitious (but super rewarding) project so we are preferably looking for very dedicated master thesis students. In case you should be interested as part of a semester thesis we can try to find a suitable subset (for example just the re-naming logic) on which you can work.
- Strong interest in computer architecture
- Experience with HDLs (preferably SystemVerliog) such as taught in VLSI I
- Knowledge of ASIC tool flow (Synthesis) or parallel enrollment with VLSI II
Composition: 30% Architecture specification, 40% Verification, 30% RTL Implementation
-  https://github.com/openhwgroup/cva6
-  http://www.ece.mtu.edu/faculty/rmkieckh/cla/4173/REFERENCES/MIPS-R10K-uman1.pdf
-  http://www.archive.ece.cmu.edu/~ece447/s13/lib/exe/fetch.php?media=21264hrm.pdf
-  https://github.com/openpower-cores/a2o
-  https://docs.boom-core.org/en/latest/
-  https://carrv.github.io/2020/papers/CARRV2020_paper_15_Zhao.pdf
-  https://people.csail.mit.edu/emer/papers/1998.06.isca.storesets.pdf