OpenRISC SoC for Sensor Applications
At the IIS we have started developing our own implementation of the OpenRISC core available from the Opencores community. A brand new optimized implementation of the OpenRisc was completed as part of a previous semester thesis. We are already using this core in our multi-core projects and we continue to make improvements.
We also have several projects that deal with acquiring data from sensors. We would like to expand our OpenRISC core with the following capabilities so that a standalone small system can be designed that can directly interface with various sensors and can communicate over low-power wireless channels.
- Wakeup radio
- For low power operations, we would like to shutdown most of the system including the processor, and wait until there is an event that requires the attention of the processor. The wake-up radio will listen to the RF interface and will detect if there is a radio transmission addressing the current sensor node. If this is the case, it will initiate the procedure that will activate the OpenRISC processor. At the same time, during this wake up it will store the incoming message and allowing the processor to access the incoming data and react to it.
- SPI interface
- SPI is used as a standard interface in many applications, especially in resource limited systems where the number of I/O pins are limited. We already have a simple implementation and would like a more improved version implemented as well.
- General Purpose IO
- Most microcontrollers have a few (4-16) general purpose pins that can be configured through software as inputs and outputs allowing low level communication with the environment. We want to add a small configurable IP that adds this capability to our current OpenRISC system.
- I2C interface
- The I2C interface is a serial protocol that (unlike SPI) allows multiple devices to be controlled through the same few connections. However, it is slightly more complex because of that. If possible we would also like to add an I2C interface to the OpenRISC processor.
The goal of the project is to make a minimal SoC that contains the OpenRISC core, sufficient memory to run example applications, the wake up radio that will listen to a wireless interface and wake-up the remaining system when necessary, and add a small set of interfaces that will allow it to connect to simple target applications in the sensing domain.
At the moment, the processor does not have a working interrupt system. We expect this support to be present at the start of the project. Since interrupt support is important for interfaces, it might be necessary to improve/refine the interrupt support of our OpenRISC implementation as well.
- Looking for 1-2 Semester/Master students
- Contact: Michele Magno
- VLSI I
- VLSI II (recommended)
- 20% System Design
- 60% ASIC Design
- 20% Verification