PULP - An Open Parallel Ultra-Low-Power Processing-Platform
This is a joint project between the Integrated Systems Laboratory (IIS) of ETH Zurich and the Energy-efficient Embedded Systems (EEES) group of UNIBO to develop an open, scalable Hardware and Software research platform with the goal to break the pJ/op barrier within a power envelope of a few mW.
The PULP platform is a multi-core platform achieving leading-edge energy-efficiency and featuring widely-tunable performance. The aim of PULP is to satisfy the computational demands of IoT applications requiring flexible processing of data streams generated by multiple sensors, such as accelerometers, low-resolution cameras, microphone arrays, vital signs monitors. As opposed to single-core MCUs, a parallel ultra-low-power programmable architecture allows to meet the computational requirements of these applications, without exceeding the power envelope of a few mW typical of miniaturized, battery-powered systems. Moreover, OpenMP, OpenCL and OpenVX are supported on PULP, enabling agile application porting, development, performance tuning and debugging.
Related Available Student Projects
- Physics is looking for PULP
- Enabling Standalone Operation for a Mobile Health Platform
- Design and Implementation of a multi-mode multi-master I2C Interface
- Optimal System Duty Cycling for a Mobile Health Platform
- Extend the RI5CY core with priviledge extensions
- Real-Time ECG Contractions Classification
- Monocular Vision-based Object Following on Nano-size Robotic Blimp
- A Waypoint-based Navigation System for Nano-Size UAVs in GPS-denied Environments
- Near-Memory Training of Neural Networks
- Trace Debugger for custom RISC-V Core
- Embedded Audio Source Localization Exploiting Coincidence Detection in Asynchronous Spike Streams
- Hardware Accelerators for Lossless Quantized Deep Neural Networks
- PVT Dynamic Adaptation in PULPv3
- PULPonFPGA: Lightweight Virtual Memory Support - Physically Contiguous Memory
- Fast Wakeup From Deep Sleep State
- DMA Streaming Co-processor
- Design of a Fused Multiply Add Floating Point Unit
- PULPonFPGA: Hardware L2 Cache
- Minimal Cost RISC-V core
- Design of a VLIW processor architecture based on RISC-V
- Covariant Feature Detector on Parallel Ultra Low Power Architecture
- PULPonFPGA: Lightweight Virtual Memory Support - Software Cache
- Ultra-High-Efficiency Power Supply Management for Ultra-Low-Power Systems on Chip
- Hardware Accelerator for Model Predictive Controller
- Hardware Support for IDE in Multicore Environment
- Variability Tolerant Ultra Low Power Cluster
- Kosmodrom The chip contains two instances of an improved Ariane cores (with FPUs) optimized for different operation corners
- Poseidon A chip containing both PULPissimo (updated single core microcontroller with 32-bit core) and Ariane (64 bit RISC-V core)
- Pulp v1 The first version of the PULP platform realized in 28nm FDSOI (RVT) technology with 4 parallel cores.
- Pulp v2 The second version of the PULP platform realized in 28nm FDSOI (LVT) technology with 4 parallel cores.
- Pulp v3 The third version of the PULP platform realized in 28nm FDSOI (RVT) technology with 4 parallel cores and a hardware accelerator.
- Honey Bunny PULp platform using RISC-V compliant RI5CY cores and Globalfoundries 28nm SLP technology. Four cores, 68 kBytes of TCDM and 256 kBytes of L2.
- Mr. Wolf new generation PULP system with 1 fabric controller (micro-riscy) and a cluster with eight RI5CY (RISC-V cores optimized for DSP operations) and two shared IEEE-754 FPUs.
- Mia Wallace Third generation of PULP platform, HW accelerators, body biasing FLLs, 256 kByte memory
- Fulmine Third generation of PULP platform, Convolutional accelerator, crypto accelerator, body biasing FLLs, 256 kByte memory
- Artemis 4 core PULP system including FPU.
- Hecate 4 core PULP system with 2 shared FPUs.
- Selene 4 core PULP system with 1 shared FPU using a logarithmic number system.
- Diana 4 core PULP system with FPUs designed using approximate computing techniques.
- Phoebe an improved version of Selene, 4 cores and 1 shared vectorial FPU using logarithmic number system
- Imperio single core RISC-V based PULPino system. Has the PULP DNA, but is a single core microprocessor complete with peripherals from the PULP project.
- Patronus chip with three separate single RISC-V cores. It is technically a newer PULPino (single core system)
- Scarabaeus a 64-bit system with one Ariane core, peripherals, and a new interrupt controller.
- Atomario multi-cluster system with two four-core RI5CY clusters.
- Vivosoc 2 core mixed-signal PULP system with a low-power A/D converter
- Vivosoc2 4 core mixed-signal PULP system with a low-power A/D converter, 128 kB L2,
- Vivosoc2.001 updated version of 4 core mixed-signal PULP system with a low-power A/D converter
- Vivosoc3 An even more updated version of 4 core mixed-signal PULP system with a low-power A/D converter
- Triphos Power management IC for VivoSoC
- Or10n An optimized implementation of the OpenRISC processor developed to be used within PULP.
- Sir10us A cryptographic application that uses the Or10n processor developed for PULP.
- Sid Large PULP chip with in-exact accelerators, LL version
- Diego Large PULP chip with in-exact accelerators, LVT version
- Manny Large PULP chip with in-exact accelerators, sub-threshold version
Templates and Logos
This archive contains all PULP logos below as well as inverted versions thereof for dark backgrounds (in PDF and PNG formats). Also, it includes the "Orbitron" font which has been used here.