User contributions
From iis-projects
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- 16:35, 10 December 2021 (diff | hist) . . (+69) . . Implementing DSP Instructions in Banshee (1S)
- 22:34, 19 November 2021 (diff | hist) . . (+114) . . Streaming Integer Extensions for Snitch (M)
- 22:33, 19 November 2021 (diff | hist) . . (+9,969) . . N Implementing DSP Instructions in Banshee (1S) (Created page with "<!-- Implementing DSP Instructions in Banshee (M/1S) --> = Overview = == Status: Available == * Type: Semester Thesis * Professor: Prof. Dr. L. Benini * Supervisors: ** :...")
- 16:20, 2 August 2021 (diff | hist) . . (+20) . . Fast Simulation of Manycore Systems (1S) (current)
- 16:19, 2 August 2021 (diff | hist) . . (+30) . . Fast Simulation of Manycore Systems (1S)
- 16:18, 2 August 2021 (diff | hist) . . (-8) . . Fast Simulation of Manycore Systems (1S)
- 16:18, 2 August 2021 (diff | hist) . . (-3) . . Fast Simulation of Manycore Systems (1S)
- 16:16, 2 August 2021 (diff | hist) . . (+9,702) . . N Fast Simulation of Manycore Systems (1S) (Created page with "<!-- Fast Simulation of Manycore Systems (1S) --> = Overview = == Status: Available == * Type: Semester Thesis * Professor: Prof. Dr. L. Benini * Supervisors: ** :User:Sr...")
- 16:14, 2 August 2021 (diff | hist) . . (+4) . . Efficient Synchronization of Manycore Systems (M/1S)
- 09:41, 6 July 2021 (diff | hist) . . (-4) . . Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S) (current)
- 09:41, 6 July 2021 (diff | hist) . . (-4) . . Manycore System on FPGA (M/S/G) (current)
- 23:08, 12 March 2021 (diff | hist) . . (-4) . . ISA extensions in the Snitch Processor for Signal Processing (M) (current)
- 23:07, 12 March 2021 (diff | hist) . . (0) . . Transforming MemPool into a CGRA (M)
- 23:06, 12 March 2021 (diff | hist) . . (+4) . . Transforming MemPool into a CGRA (M)
- 17:47, 15 February 2021 (diff | hist) . . (+18) . . Physical Implementation of Ara, PULP's Vector Machine (1-2S)
- 10:50, 5 February 2021 (diff | hist) . . (+13) . . Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
- 10:46, 5 February 2021 (diff | hist) . . (+22) . . Manycore System on FPGA (M/S/G)
- 17:03, 31 January 2021 (diff | hist) . . (-7) . . Manycore System on FPGA (M/S/G)
- 17:02, 31 January 2021 (diff | hist) . . (+4) . . Manycore System on FPGA (M/S/G) (→Project Description)
- 17:02, 31 January 2021 (diff | hist) . . (0) . . Manycore System on FPGA (M/S/G)
- 16:58, 31 January 2021 (diff | hist) . . (+1,686) . . Manycore System on FPGA (M/S/G)
- 16:18, 31 January 2021 (diff | hist) . . (0) . . N File:Mempool logo.pdf (current)
- 16:12, 31 January 2021 (diff | hist) . . (-1) . . Transforming MemPool into a CGRA (M)
- 16:12, 31 January 2021 (diff | hist) . . (-2) . . Transforming MemPool into a CGRA (M)
- 16:10, 31 January 2021 (diff | hist) . . (+4) . . Transforming MemPool into a CGRA (M) (→Introduction)
- 16:10, 31 January 2021 (diff | hist) . . (0) . . N File:Mempool cgra.png (current)
- 16:08, 31 January 2021 (diff | hist) . . (+13,058) . . N Transforming MemPool into a CGRA (M) (Created page with "<!-- Transforming MemPool into a CGRA (M) --> = Overview = == Status: Available == * Type: Master Thesis * Professor: Prof. Dr. L. Benini * Supervisors: ** :User:Sriedel...")
- 23:46, 30 January 2021 (diff | hist) . . (+6,925) . . N Manycore System on FPGA (M/S/G) (Created page with "<!-- Manycore System on FPGA --> = Overview = == Status: Available == * Type: Bachelor/Semester/Master Thesis * Professor: Prof. Dr. L. Benini * Supervisors: ** :User:Sri...")
- 18:19, 29 January 2021 (diff | hist) . . (-18) . . Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core (current)
- 18:16, 29 January 2021 (diff | hist) . . (-18) . . Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
- 18:15, 29 January 2021 (diff | hist) . . (0) . . Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
- 18:13, 29 January 2021 (diff | hist) . . (-1) . . ASIC Design Projects (→How does it work) (current)
- 18:12, 29 January 2021 (diff | hist) . . (+18) . . VLSI Implementation of a 5G Ciphering Accelerator
- 18:10, 29 January 2021 (diff | hist) . . (+18) . . Event-Driven Convolutional Neural Network Modular Accelerator (→Links) (current)
- 18:10, 29 January 2021 (diff | hist) . . (+18) . . Spiking Neural Network for Autonomous Navigation (→Links) (current)
- 18:10, 29 January 2021 (diff | hist) . . (+18) . . RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB (→Links) (current)
- 18:10, 29 January 2021 (diff | hist) . . (+18) . . Level Crossing ADC For a Many Channels Neural Recording Interface (→Links) (current)
- 18:08, 29 January 2021 (diff | hist) . . (+18) . . Resilient Brain-Inspired Hyperdimensional Computing Architectures (current)
- 18:06, 29 January 2021 (diff | hist) . . (+76) . . ASIC Design Projects (→Newly available ASIC design projects from our group)
- 18:05, 29 January 2021 (diff | hist) . . (+1) . . Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core (current)
- 18:03, 29 January 2021 (diff | hist) . . (-108) . . ASIC Development of 5G-NR LDPC Decoder
- 13:28, 28 January 2021 (diff | hist) . . (+328) . . ASIC Design Projects
- 23:25, 27 January 2021 (diff | hist) . . (+33) . . Digital (→Topic List)
- 23:22, 27 January 2021 (diff | hist) . . (+18) . . Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
- 23:21, 27 January 2021 (diff | hist) . . (+156) . . ASIC Design Projects
- 23:39, 23 January 2021 (diff | hist) . . (0) . . User:Sriedel (current)
- 18:07, 20 January 2021 (diff | hist) . . (-4) . . MemPool on HERO (1S) (current)
- 18:04, 20 January 2021 (diff | hist) . . (+12,430) . . N Efficient Synchronization of Manycore Systems (M/1S) (Created page with "<!-- Eliminating the polling of locks (M/1S) --> = Overview = == Status: Available == * Type: Semester/Master Thesis * Professor: Prof. Dr. L. Benini * Supervisors: ** :U...")
- 11:07, 20 January 2021 (diff | hist) . . (+21) . . An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
- 11:07, 20 January 2021 (diff | hist) . . (0) . . m Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
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