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Showing below up to 50 results in range #1 to #50.

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  1. (M/1-2S): A Snitch-based Compute Accelerator for HERO →‎ A Snitch-based Compute Accelerator for HERO (M/1-2S)
  2. 3D Turbo Coder ASIC Realization →‎ 3D Turbo Decoder ASIC Realization
  3. 3D Turbo Codes →‎ 3D Turbo Coder ASIC Realization
  4. A Hardware Architecture for Real-Time Saliency Estimation →‎ Accelerator for Spatio-Temporal Video Filtering
  5. A Wireless Sensor Network for a Smart LED Lighing control →‎ A Wireless Sensor Network for a Smart LED Lighting control
  6. Ab-initio Quantum Transport Simulation of Hetero-Bilayer Tunnel Field-Effect Transistors →‎ Quantum transport in 2D heterostructures
  7. Advanced Repetition Combining →‎ Advanced 5G Repetition Combining
  8. An FPGA-Based Testbed for 4G/LTE Mobile Communication →‎ Baseband Processor Development for 4G IoT
  9. Autonomous Smart Sensors for IoT →‎ Category:SmartSensors
  10. BLISS →‎ BLISS - Battery-Less Identification System for Security
  11. Bateryless Imaging Neural Network →‎ Convolutional Neural Networks in Bateryless Nodes
  12. Belfanti →‎ User:Belfanti
  13. Build the Fastest 2G Modem →‎ Build the Fastest 2G Modem Ever
  14. Cell Measurements for the Internet of Things →‎ Cell Measurements for the 5G Internet of Things
  15. Channel Shortening ASIC →‎ Channel Shortening Prefilter
  16. Channel Shortening Prefilter →‎ VLSI Implementation of a Channel Shortener
  17. Coherence-Capable Write-Back L1 Data Cache for Ariane →‎ Coherence-Capable Write-Back L1 Data Cache for Ariane (M)
  18. Convolutional Network Accelerator →‎ Design and Implementation of a Convolutional Neural Network Accelerator ASIC
  19. Convolutional Neural Networks in Bateryless Nodes →‎ Gomeza old project4
  20. Cryogenic measurements and modeling of electrical devices →‎ Design space exploration of InP Heterojunction Bipolar Transistors (DHBTs)
  21. Deep-Learning Phoneme Recognition from a Ultra-Low Power Spiking Cochlea →‎ Deep-Learning Based Phoneme Recognition from a Ultra-Low Power Spiking Cochlea
  22. Design and Implementation of a multi-mode multi-master I2C Interface →‎ Design and Implementation of a multi-mode multi-master I2C peripheral
  23. Design and VLSI Implementation of a Constrained-Viterbi Algorithm for 3GPP TD-HSPA →‎ Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA
  24. Digital Audio High Level Synthesis →‎ Digital Audio High Level Synthesis for FPGAs
  25. Digital Audio High Level Synthesis for FPGAs →‎ Digital Audio Processor for Cellular Applications
  26. Digital Beamforming ASIC for 3D Ultrasound Imaging →‎ Digital Beamforming for Ultrasound Imaging
  27. Digital Front End Design for Narrowband LTE Systems →‎ Time and Frequency Synchronization in LTE Cat-0 Devices
  28. Digital Transmitter Mobile Communications →‎ Digital Transmitter for Mobile Communications
  29. EDGE Evolution Protocol Analyzer →‎ Open Source Baseband Firmware for 2G Cellular Networks
  30. Electron conductance of lithiated SnO2-based anode materials →‎ Electron conductance of lithiated SnO₂ -based anode materials for Li-ion batteries
  31. Electron conductance of lithiated SnO₂ -based anode materials for Li-ion batteries →‎ Stable nonvolatile resistance switching (NVRS) in single-layer 2D Materials
  32. Elliptic Curve Accelerator for zkSNARKS →‎ Elliptic Curve Accelerator for zkSNARKs
  33. Energy Efficient Heterogeneous MCU Platforms →‎ Gomeza old project1
  34. Energy Efficient Heterogeneous Sensor Nodes →‎ Gomeza old project3
  35. Energy Netural Multi Sensors Wearable Device →‎ Energy Neutral Multi Sensors Wearable Device
  36. EvaLTE →‎ EvaLTE: A 2G/3G/4G Cellular Transceiver FMC
  37. EvalEDGE →‎ EvalEDGE: A 2G Cellular Transceiver FMC
  38. Event Driven Spike sorting engine →‎ Ternary Weights Engine For Efficient Many Channels Spike Sorting Applications
  39. Fast Data Interface →‎ Data Interface: SPI to PC Bridge for ASICs
  40. Fast Wakeup →‎ Fast Wakeup From Deep Sleep State
  41. Fault Tolerant OpenPULP System for Critical Spacial Applications →‎ PULP in space - Fault Tolerant PULP System for Critical Space Applications
  42. First ASIC Realization For A New HSPA/HSPA+ Detector →‎ Design and VLSI Implementation of a Constrained-Viterbi Algorithm for 3GPP TD-HSPA
  43. GPU-Accelerated Nanoelectronic Device Simulations →‎ Investigation of Redox Processes inCBRAM
  44. HERO: TLB Coherency →‎ HERO: TLB Invalidation
  45. Heterogeneous Acceleration Systems →‎ Heterogeneous SoCs
  46. Heterogeneous Microcontroller for Batteryless Applications →‎ Energy Efficient Heterogeneous Sensor Nodes
  47. High-Definition 3D Ultrasound Imaging ASIC →‎ Efficient Digital Signal Processing in High-Channel-Count High-Frame-Rate 3D Ultrasound Imaging Systems
  48. High-Throughput Next Generation Turbo Decoders →‎ ASIC Implementation of High-Throughput Next Generation Turbo Decoders
  49. High performance continous-time Delta-Sigma ADC for magnetic resonance imaging →‎ High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging
  50. High performance continous-time Delta-Sigma ADC for mobile communications →‎ High performance continous-time Delta-Sigma ADC for magnetic resonance imaging

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