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Ternary Weights Engine For Efficient Many Channels Spike Sorting Applications

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Over the last five decades, the number of simultaneously recorded neurons has doubled approximately every 7 year [Stevenson2011]. This trend motivates researchers to find new approaches to analyse and process the increasing amount of collected data, which grows linearly with the number of recording channels. Implantable Multi Electrode Arrays (MEAs) are becoming more and more dense, reaching a spatial resolution smaller than the physical distance between neurons. Contrarily to what happens in neural recording employing tetrodes, in this scenario, the data streams that reflect the underlying neuron activity can present high spatial correlation among neighboring channels. This poses new challenges related to data acquisition and processing of those signals, since standard spike sorting approaches can not efficiently employed anymore.

Project description

The goal of this project is to explore new algorithms for spike sorting, capable to exploit the intrinsic correlations among neighboring channels in Multi Electrode Arrays. The algorithm should be capable to identify the activity of a single neuron, and separate it from the activity of close-by neurons. In this project we target implantable applications (e.g. Brain Machine Interfaces), therefore the available power budget allocated for the algorithm execution is highly constrained by the amount of power that can be dissipated by brain tissues. In order to achieve this goal, in a second phase of the project we aim at designing a dedicated hardware engine operating on MEAs data streams.

The student is required to:

  • Evaluate different algorithms and select the most suitable for the proposed application
  • propose a hardware implementation for the algorithm
  • Verify the implementation
  • Evaluate Power/Performance/Area of the proposed implementation.

Required Skills

To work on this project, you will need:

  • to have worked in the past with at least one RTL language (SystemVerilog or Verilog or VHDL) - having followed the VLSI1 / VLSI2 courses is recommended
  • basic familiarity with a scripting language for deep learning (Python or Lua…)
  • a lot of patience!
  • to be strongly motivated for a difficult but super-cool project

If you want to work on this project, but you think that you do not match some the required skills, we can give you some preliminary exercise to help you fill in the gap.

Status: Completed

Supervision: Alfio Di Mauro
Supervision: Francesco Conti


Luca Benini

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Practical Details

Meetings & Presentations

The students and advisor(s) agree on weekly meetings to discuss all relevant decisions and decide on how to proceed. Of course, additional meetings can be organized to address urgent issues.

Around the middle of the project there is a design review, where senior members of the lab review your work (bring all the relevant information, such as prelim. specifications, block diagrams, synthesis reports, testing strategy, ...) to make sure everything is on track and decide whether further support is necessary. They also make the definite decision on whether the chip is actually manufactured (no reason to worry, if the project is on track) and whether more chip area, a different package, ... is provided. For more details confer to [1].

At the end of the project, you have to present/defend your work during a 15 min. presentation and 5 min. of discussion as part of the IIS colloquium.


  • [Stevenson2011] How advances in neural recording affect data analysis [2]
  • [Rovere2017] A 2.2 µW Cognitive Always-On Wake-Up Circuit for Event-Driven Duty-Cycling of IoT Sensor Nodes [3]
  • [Liu2018] Event-driven processing for hardware-efficient neural spike sorting [4]


  • The EDA wiki with lots of information on the ETHZ ASIC design flow (internal only) [5]
  • The IIS/DZ coding guidelines [6]

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