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The current proposal corresponds to a brute-force approach to combining this information. As a first step in your project, you will study ways to reduce the complexity on an algorithmic level. Based on this, you will come up with an efficient architecture to implement this algorithm. You can either design an ASIC with only this block, or integrate it into our RF SoC and test it on an FPGA.
 
The current proposal corresponds to a brute-force approach to combining this information. As a first step in your project, you will study ways to reduce the complexity on an algorithmic level. Based on this, you will come up with an efficient architecture to implement this algorithm. You can either design an ASIC with only this block, or integrate it into our RF SoC and test it on an FPGA.
  
 +
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===Status: Available ===
 
===Status: Available ===
 
: Looking for 1-2 Semester/Master students
 
: Looking for 1-2 Semester/Master students
 
: Contact: [[:User:Lstefan | Stefan Lippuner]]
 
: Contact: [[:User:Lstefan | Stefan Lippuner]]
===Prerequisites===
+
--->
: An interest in wireless communication and signal processing
 
: Matlab programming experience
 
: VHDL experience (VLSI I lecture)
 
 
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===Status: Completed ===
 
===Status: Completed ===
Line 21: Line 19:
 
: Matthias Baer, Renzo Andri
 
: Matthias Baer, Renzo Andri
 
--->
 
--->
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===Status: In Progress ===
 
===Status: In Progress ===
 
: Student A, StudentB
 
: Student A, StudentB
 
: Supervision: [[:User:Lstefan | Stefan Lippuner]]
 
: Supervision: [[:User:Lstefan | Stefan Lippuner]]
--->
+
===Prerequisites===
 +
: An interest in wireless communication and signal processing
 +
: Matlab programming experience
 +
: VHDL experience (VLSI I lecture)
  
 
===Character===
 
===Character===

Latest revision as of 14:50, 17 August 2020

PBCH/MIB Repetitions. Image source: [2].

Introduction

LTE Cat-M1 (eMTC) is a 5G standard optimized for low energy consumption and excellent coverage. We're currently developing a modem for the Cat-M1 standard. One of the most challenging parts of designing a Cat-M1 IoT modem is improving the coverage by 20 dB. For the so-called PBCH this is especially difficult, since it has not been changed from legacy LTE. While it is transmitted continuously, the data changes every 40 ms. One idea is combining the information of these repetitions, even though they contain changed data [1].

Project Description

The current proposal corresponds to a brute-force approach to combining this information. As a first step in your project, you will study ways to reduce the complexity on an algorithmic level. Based on this, you will come up with an efficient architecture to implement this algorithm. You can either design an ASIC with only this block, or integrate it into our RF SoC and test it on an FPGA.

Status: In Progress

Student A, StudentB
Supervision: Stefan Lippuner

Prerequisites

An interest in wireless communication and signal processing
Matlab programming experience
VHDL experience (VLSI I lecture)

Character

30% Theory, Algorithms and Simulation
40% Hardware Design (HLS/VHDL)
30% FPGA Verification / ASIC implementation


Professor

Qiuting Huang

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Related Projects

RF SoCs for the Internet of Things

References

[1] Sierra Wireless. R1-131043: PBCH Correlation Decoder.

[2] All about Wired and Wireless Technology. http://www.simpletechpost.com/2012/06/master-information-block-mib-in-lte.html.

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