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Projects that are part of the analog and mixed signal design group.
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= Analog and Mixed Signal Design Group =
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The Analog and Mixed Signal Design Group is specialized in designing mixed signal integrated circuits and systems. The group divides into following research fields:
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====[[Analog IC Design|Analog IC Design]]====
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The focus of Analog IC Design projects is on designing analog circuits, simulations and layout. The applications cover a wide range: from high-speed transceivers to power management circuits, PLL design and bio-medical front-ends to name a few.
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====[[Biomedical System on Chips|Biomedical System on Chips]]====
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Most projects are based around our bio-medical SoC called ''VivoSoC''. It consists of specialised analogue front-ends (e.g. for ExG or neural signal acquisition, PPG based measurements, neural stimulation etc.) as well as powerful, PULP-based processor cores. Applications are in the field of optogenetics stimulation, ExG recordings (wearable and implantable), in-vivo and in-vitro experiments, neuroprosthetics etc.
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====[[RF SoCs for the Internet of Things|RF SoCs for the Internet of Things]]====
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We design digital signal processing accelerators for highly integrated RF SoCs in the field of wireless communication. Our current platform with a multi-core processor system and a great RF transceiver allows us to research upcoming wireless transmission standards. One of our current focus areas is 5G cellular communication for the Internet of Things, where we offer many interesting projects for students.  
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====[[High-Performance & V2X Cellular Communications|High-Performance & V2X Cellular Communications]]====
  
==Available Projects==
 
<DynamicPageList>
 
suppresserrors = true
 
category = Available
 
category = Analog
 
</DynamicPageList>
 
  
[[RF SoCs for the Internet of Things|Digital design projects]] in the area of telecommunications are also available.
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=Available Projects=
  
==Active Projects==
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===[[Analog IC Design|Analog IC Design]]===
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[[File:times_adpll.png|thumb|200px|TimesADPLL: A power efficient wide loop bandwidth fractional-N all digital PLL]]
 
<DynamicPageList>
 
<DynamicPageList>
 
suppresserrors = true
 
suppresserrors = true
category = In progress
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category = Available
 
category = Analog
 
category = Analog
</DynamicPageList>
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category = Analog IC Design
==Completed Projects==
 
===2017===
 
<DynamicPageList>
 
suppresserrors = true
 
category = Completed
 
category = Analog
 
category = 2017
 
</DynamicPageList>
 
<DynamicPageList>
 
suppresserrors = true
 
category = Completed
 
category = Telecommunications
 
category = 2017
 
 
</DynamicPageList>
 
</DynamicPageList>
  
===2016===
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===[[Biomedical System on Chips|Biomedical System on Chips]]===
<DynamicPageList>
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[[File:vivosoc3_micrograph.png|thumb|200px|VivoSoC 3: A Multi-Sensor and Parallel Processing SoC for Miniaturised Medical Instrumentation]]
suppresserrors = true
 
category = Completed
 
category = Analog
 
category = 2016
 
</DynamicPageList>
 
<DynamicPageList>
 
suppresserrors = true
 
category = Completed
 
category = Telecommunications
 
category = 2016
 
</DynamicPageList>
 
  
===2015===
 
 
<DynamicPageList>
 
<DynamicPageList>
 
suppresserrors = true
 
suppresserrors = true
category = Completed
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category = Available
 
category = Analog
 
category = Analog
category = 2015
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category = Biomedical System on Chips
</DynamicPageList>
 
<DynamicPageList>
 
suppresserrors = true
 
category = Completed
 
category = Telecommunications
 
category = 2015
 
 
</DynamicPageList>
 
</DynamicPageList>
  
===2014===
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===[[RF SoCs for the Internet of Things|RF SoCs for the Internet of Things]]===
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[[File:Rfsoc_board_chip.png|thumb|200px|Our RF SoC with support for cellular communication and positioning.]]
 
<DynamicPageList>
 
<DynamicPageList>
 
suppresserrors = true
 
suppresserrors = true
category = Completed
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category = Available
category = Analog
 
category = 2014
 
</DynamicPageList>
 
<DynamicPageList>
 
suppresserrors = true
 
category = Completed
 
 
category = Telecommunications
 
category = Telecommunications
category = 2014
 
 
</DynamicPageList>
 
</DynamicPageList>
  
===2013===
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===[[High-Performance & V2X Cellular Communications|High-Performance & V2X Cellular Communications]]===
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[[File:C-v2x-data.jpg|thumb|200px|© Continental AG]]
 
<DynamicPageList>
 
<DynamicPageList>
 
suppresserrors = true
 
suppresserrors = true
category = Completed
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category = Available
category = Analog
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category = Wireless Communications
category = 2013
 
</DynamicPageList>
 
===2012===
 
<DynamicPageList>
 
suppresserrors = true
 
category = Completed
 
category = Analog
 
category = 2012
 
 
</DynamicPageList>
 
</DynamicPageList>

Revision as of 13:54, 6 December 2018


Analog and Mixed Signal Design Group

The Analog and Mixed Signal Design Group is specialized in designing mixed signal integrated circuits and systems. The group divides into following research fields:

Analog IC Design

The focus of Analog IC Design projects is on designing analog circuits, simulations and layout. The applications cover a wide range: from high-speed transceivers to power management circuits, PLL design and bio-medical front-ends to name a few.

Biomedical System on Chips

Most projects are based around our bio-medical SoC called VivoSoC. It consists of specialised analogue front-ends (e.g. for ExG or neural signal acquisition, PPG based measurements, neural stimulation etc.) as well as powerful, PULP-based processor cores. Applications are in the field of optogenetics stimulation, ExG recordings (wearable and implantable), in-vivo and in-vitro experiments, neuroprosthetics etc.

RF SoCs for the Internet of Things

We design digital signal processing accelerators for highly integrated RF SoCs in the field of wireless communication. Our current platform with a multi-core processor system and a great RF transceiver allows us to research upcoming wireless transmission standards. One of our current focus areas is 5G cellular communication for the Internet of Things, where we offer many interesting projects for students.

High-Performance & V2X Cellular Communications

Available Projects

Analog IC Design

TimesADPLL: A power efficient wide loop bandwidth fractional-N all digital PLL


Biomedical System on Chips

VivoSoC 3: A Multi-Sensor and Parallel Processing SoC for Miniaturised Medical Instrumentation


RF SoCs for the Internet of Things

Our RF SoC with support for cellular communication and positioning.


High-Performance & V2X Cellular Communications

© Continental AG