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Analog Layout Engine

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Analog Layout Engine.png

Short Description

While digital circuit layouts are highly supported by CAD programs, leading to short production and verification times, analog circuit design remains time consuming. Drawing the layout even for small analog circuits takes up to several weeks.

This project aims at developing a solution to greatly simplify the layout process. After analyzing the circuit and layout of OTAs (Operational Transconductance Amplifiers), which are inherently symmetrical and scalable structures, tools will be developed using one or several programming languages to automatically generate parametrized cells (PCELLS) in Cadence.

Status: Available

Looking for 1-2 Semester/Master students
Contact: Schekeb Fateh

Prerequisites

AIC

Character

20% Theory
40% Circuit Design
40% Programming

Professor

Qiuting Huang

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Detailed Task Description

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