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Application Specific Frequency Synthesizers (Analog/Digital PLLs)

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Short Description

Various aspects of a frequency synthesizers have been widely investigated for several decades, such as output phase noise, output frequency range, locking time, supply rejection, tolerance to variabilities, spur minimization and input noise rejection. Consequently, numerous innovations have been introduced for improving the performance such as sub-sampling PLL, Multiplying DLL, replica-biasing, DSM noise cancellation, digital-to-time converter based fractional-N synthesis, injection locking and so on. Therefore, a recent frequency synthesizer is highly well-optimized so that its performance is closed to the theoretical limits. In this project, students will learn the key techniques for an advanced frequency synthesizer by designing a frequency synthesizer specific to the application requirements.

Status: Available

Looking for 1-2 Semester or master students
Contact: Prof. Taekwang Jang <>


Basic knowledge in analog circuit design

Available Projects

Ultra low noise frequency synthesizers for 5G LTE
Frequency synthesis for digital circuits
Spread spectrum PLLs
Inductor-less low noise frequency synthesizers


30% Theory
30% Simulation
40% Circuit design


Taekwang Jang

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