Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development
In instruction-based programmable architectures, the key challenge is how to mitigate the Von Neumann Bottleneck (VNB). This is related with the memory traffic required to the instruction fetch. Multi-core designs, although highly flexible, do not explore the regularity of regularity of data-parallel applications. Each core tends to execute the same instruction many times, a waste in terms of both area and energy.
The quest for extreme energy efficiency in data-parallel execution revamped the interest on vector architectures. Such systems promise to tackle the VNB very effectively, providing better energy efficiency than a general purpose processor for applications that fit its execution model. The renewed interest in vector processing is reflected by the instruction of vector instruction extensions in all popular Instruction Set Architectures, such as ARM's with its SVE, and RISC-V with the V Extension.
Within the PULP Project, Ara is a parametric in-order high-performance 64-bit vector unit based on the version 0.5-Draft of the RISC-V vector extension. The vector unit was design for a memory bandwidth per peak performance ratio of 2B/DP-FLOP. Ara works in tandem with Ariane, an open-source application-class RV64GC scalar core. The vector unit supports mixed-precision arithmetic with double, single, and half-precision floating point operands.
Since Ara has been published, new versions of the RISC-V V Extension have been published. The goal of this project is to update Ara so that it is compliant with the newest specifications.
The project can be done by as two semester thesis or a Master's thesis. The project consists of the following parts:
1. Familiarizing with the RISC-V Vector Extension and the Ara source code. (~2 person weeks)
2. Update Ariane's frontend, so that it decodes the new vector instructions. (~2 person weeks)
3. Update Ara's backend with the updated instructions. (~4 person weeks)
4. Validate the design by co-simulating it with a RISC-V Simulator. (~2 person weeks)
5. Documentation and report writing (~2 person week)
Depending on timing constraints and if the student(s) are interested, a tape-out of the updated design might be feasible.
To work on this project, you will need:
- to have worked in the past with at least one RTL language (SystemVerilog or Verilog or VHDL). Having followed the VLSI I course is highly recommended.
- to have prior knowledge of hardware design and computer architecture
- to be motivated to work hard on a super cool open-source project
- Looking for one or two semester projects
- Supervision: Matheus Cavalcante
Meetings & Presentations
The students and advisor(s) agree on weekly meetings to discuss all relevant decisions and decide on how to proceed. Of course, additional meetings can be organized to address urgent issues.
Around the middle of the project there is a design review, where senior members of the lab review your work (bring all the relevant information, such as prelim. specifications, block diagrams, synthesis reports, testing strategy, ...) to make sure everything is on track and decide whether further support is necessary. They also make the definite decision on whether the chip is actually manufactured (no reason to worry, if the project is on track) and whether more chip area, a different package, ... is provided. For more details refer to (1).
At the end of the project, you have to present/defend your work during a 15 min. presentation and 5 min. of discussion as part of the IIS Colloquium.
- Matheus Cavalcante, Fabian Schuiki, Florian Zaruba, Michael Schaffner, Luca Benini. Ara: A 1GHz+ Scalable and Energy-Efficient RISC-V Vector Processor with Multi-Precision Floating Point Support in 22nm FD-SOI. link