Difference between revisions of "Benjamin Weber"
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Benjamin Weber received his BSc and MSc in Electrical Engineering and | Benjamin Weber received his BSc and MSc in Electrical Engineering and | ||
Information Technology from the Swiss Federal Institute of Technology | Information Technology from the Swiss Federal Institute of Technology | ||
| − | (ETH) in August 2010 and in June 2012, respectively. | + | (ETH) in August 2010 and in June 2012, respectively. In 2017 he completed |
| − | PhD | + | his PhD thesis entitled "An Evolved EDGE System on Chip for the Cellular |
| − | Engineering (D-ITET) at ETH, more particularly, at the Integrated Systems | + | Internet of Things" at the Department of Information Technology and |
| − | Laboratory (IIS). | + | Electrical Engineering (D-ITET) at ETH, more particularly, at the |
| − | + | Integrated Systems Laboratory (IIS). The thesis was defended successfully | |
| − | + | and he received his PhD in November 2018. For more details see [https://www.linkedin.com/in/benjamin-weber-2300b0169/ Benjamin Weber's LinkedIn profile]. | |
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==Completed Projects== | ==Completed Projects== | ||
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category = Weberbe | category = Weberbe | ||
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Latest revision as of 17:17, 30 November 2021
Short Bio
Benjamin Weber received his BSc and MSc in Electrical Engineering and Information Technology from the Swiss Federal Institute of Technology (ETH) in August 2010 and in June 2012, respectively. In 2017 he completed his PhD thesis entitled "An Evolved EDGE System on Chip for the Cellular Internet of Things" at the Department of Information Technology and Electrical Engineering (D-ITET) at ETH, more particularly, at the Integrated Systems Laboratory (IIS). The thesis was defended successfully and he received his PhD in November 2018. For more details see Benjamin Weber's LinkedIn profile.
Completed Projects
- Interference Cancellation for EC-GSM-IoT
- Sub Noise Floor Channel Estimation for the Cellular Internet of Things
- Internet of Things SoC Characterization
- VLSI Implementation of a Low-Complexity Channel Shortener for 2G EC-GSM-IoT and Evolved EDGE
- Internet of Things Network Synchronizer
- WCDMA/HSPA+ Synchronization System Design, Implementation, and Testing
- System Analysis and VLSI Design of NB-IoT Baseband Processing
- Digital Transmitter for Mobile Communications
- FPGA-Based Digital Frontend for 3G Receivers
- EvaLTE: A 2G/3G/4G Cellular Transceiver FMC
- Synchronisation and Cyclic Prefix Handling For LTE Testbed
- An FPGA-Based Testbed for 3G Mobile Communications Receivers
- Reading The GSM Beacon Carrier with OsmocomBB and stoneEDGE
- Baseband Meets CPU
- StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC
- EvalEDGE: A 2G Cellular Transceiver FMC
- RazorEDGE: An Evolved EDGE DBB ASIC
- Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA
- Time and Frequency Synchronization in LTE Cat-0 Devices
- Evolved EDGE Physical Layer Incremental Redundancy Architecture
- MatPHY: An Open-Source Physical Layer Development Framework
