Difference between revisions of "Benjamin Weber"
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| + | ==Short Bio== | ||
| + | Benjamin Weber received his BSc and MSc in Electrical Engineering and | ||
| + | Information Technology from the Swiss Federal Institute of Technology | ||
| + | (ETH) in August 2010 and in June 2012, respectively. Currently, he is a | ||
| + | PhD student at the Department of Information Technology and Electrical | ||
| + | Engineering (D-ITET) at ETH, more particularly, at the Integrated Systems | ||
| + | Laboratory (IIS). His research interests include low-power physical layer | ||
| + | architectures, open-source protocol stacks, and cross-layer optimization | ||
| + | for Machine-to-Machine (M2M) and Internet-of-Things (IoT) type cellular | ||
| + | communications. | ||
==Available Projects== | ==Available Projects== | ||
<DynamicPageList> | <DynamicPageList> | ||
Revision as of 10:38, 10 March 2015
Contents
Short Bio
Benjamin Weber received his BSc and MSc in Electrical Engineering and Information Technology from the Swiss Federal Institute of Technology (ETH) in August 2010 and in June 2012, respectively. Currently, he is a PhD student at the Department of Information Technology and Electrical Engineering (D-ITET) at ETH, more particularly, at the Integrated Systems Laboratory (IIS). His research interests include low-power physical layer architectures, open-source protocol stacks, and cross-layer optimization for Machine-to-Machine (M2M) and Internet-of-Things (IoT) type cellular communications.
Available Projects
No pages meet these criteria.
Projects in Progress
No pages meet these criteria.
Completed Projects
- Interference Cancellation for EC-GSM-IoT
- Sub Noise Floor Channel Estimation for the Cellular Internet of Things
- Internet of Things SoC Characterization
- VLSI Implementation of a Low-Complexity Channel Shortener for 2G EC-GSM-IoT and Evolved EDGE
- Internet of Things Network Synchronizer
- WCDMA/HSPA+ Synchronization System Design, Implementation, and Testing
- System Analysis and VLSI Design of NB-IoT Baseband Processing
- Digital Transmitter for Mobile Communications
- FPGA-Based Digital Frontend for 3G Receivers
- EvaLTE: A 2G/3G/4G Cellular Transceiver FMC
- Synchronisation and Cyclic Prefix Handling For LTE Testbed
- An FPGA-Based Testbed for 3G Mobile Communications Receivers
- Reading The GSM Beacon Carrier with OsmocomBB and stoneEDGE
- Baseband Meets CPU
- StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC
- EvalEDGE: A 2G Cellular Transceiver FMC
- RazorEDGE: An Evolved EDGE DBB ASIC
- Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA
- Time and Frequency Synchronization in LTE Cat-0 Devices
- Evolved EDGE Physical Layer Incremental Redundancy Architecture
- MatPHY: An Open-Source Physical Layer Development Framework
Contact Information
- Office: ETZ J71.2
- e-mail: weberbe@iis.ee.ethz.ch
- phone: +41 44 632 4491
