Brunn test

• MemPool on HERO (1S)
• NVDLA meets PULP
• Hardware Accelerators for Lossless Quantized Deep Neural Networks
• Energy-Efficient Brain-Inspired Hyperdimensional Computing
• A Recurrent Neural Network Speech Recognition Chip
• Implementation of a Heterogeneous System for Image Processing on an FPGA (S)
• Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development
• Deep Convolutional Autoencoder for iEEG Signals
• Ibex: FPGA Optimizations
• Ibex: Bit-Manipulation Extension
• Floating-Point Divide & Square Root Unit for Transprecision
• Exploring features and algorithms for ultra-low-power closed-loop systems for epilepsy control
• TCNs vs. LSTMs for Embedded Platforms
• An Energy Efficient Brain-Computer Interface using Mr.Wolf
• Timing Channel Mitigations for RISC-V Cores
• A computational memory unit using phase-change memory devices
• Real-Time Embedded Classification of Neural Activity in Rat Barrel Cortex
• Real-Time ECG Contractions Classification
• Toward hyperdimensional active perception: learning compressed sensorimotor control by demonstration
• Exploring Algorithms for Early Seizure Detection
• HERO: TLB Invalidation
• Ternary Weights Engine For Efficient Many Channels Spike Sorting Applications
• Indoor Positioning with Bluetooth
• Improving Resiliency of Hyperdimensional Computing
• Toward Superposition of Brain-Computer Interface Models
• Predictable Execution on GPU Caches
• Freedom from Interference in Heterogeneous COTS SoCs
• Analysis and Design of Power Efficient RF/ mm-Wave LC-tank Oscillator in 28nm for 5G communication applications
• CMOS power amplifier for field measurements in MRI systems
• Ultra-low power sampling front-end for acquisition of physiological signals
• Switched-capacitor power amplifier for IoT mobile communications: design of signal processing path
• Deep Learning for Brain-Computer Interface
• LightProbe - WIFI extension (PCB)
• Digital Audio Interface for Smart Intensive Computing Triggering
• Trace Debugger for custom RISC-V Core
• Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration
• Turbo Equalization for Cellular IoT
• Shared Correlation Accelerator for an RF SoC
• IoT Turbo Decoder
• BigPULP: Shared Virtual Memory Multicluster Extensions
• Sensor Fusion for Rockfall Sensor Node
• Development of a Rockfall Sensor Node
• FPGA Optimizations of Dense Binary Hyperdimensional Computing
• Fast and Accurate Multiclass Inference for Brain–Computer Interfaces
• Intelligent Power Management Unit (iPMU)
• Ultrafast Medical Ultrasound imaging on a GPU
• LightProbe - Implementation of compressed-sensing algorithms
• A Wireless Sensor Network for a Smart Building Monitor and Control
• Creating a HDMI Video Interface for PULP
• Standard Cell Compatible Memory Array Design
• Efficient NB-IoT Uplink Design
• Interference Cancellation for EC-GSM-IoT
• A Wireless Sensor Network for HPC monitoring
• Linux Driver for built-in ADC using DMA and Programmable Real-Time Unit (PRU) support on Beaglebone Black used as embedded HPC-performance-monitoring device
• Signal-Processing and Data-Compression on Beaglebone Black used as embedded HPC-performance-monitoring device
• Towards Self-Sustainable Unmanned Aerial Vehicles
• Study and Development of Intelligent Capability for Small-Size UAVs
• Towards Autonomous Navigation for Nano-Blimps
• PULP-Shield for Autonomous UAV
• Self-Learning Drones based on Neural Networks
• BigPULP: Multicluster Synchronization Extensions
• LTE-Advanced RF Front-end Design in 28nm CMOS Technology
• Design of low-offset dynamic comparators
• Switched Capacitor Based Bandgap-Reference
• Smart Virtual Memory Sharing
• Sub Noise Floor Channel Estimation for the Cellular Internet of Things
• Hardware Accelerated Derivative Pricing
• Internet of Things SoC Characterization
• VLSI Implementation of a Low-Complexity Channel Shortener for 2G EC-GSM-IoT and Evolved EDGE
• Glitches Reduce Listening Time of Your iPod
• Internet of Things Network Synchronizer
• PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker
• Accelerator for Boosted Binary Features
• Accelerator for Spatio-Temporal Video Filtering
• High performance continous-time Delta-Sigma ADC for biomedical applications
• Charging System for Implantable Electronics
• GUI-developement for an action-cam-based eye tracking device
• Ultra Low-Power Oscillator
• WCDMA/HSPA+ Synchronization System Design, Implementation, and Testing
• Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea
• Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors
• System Analysis and VLSI Design of NB-IoT Baseband Processing
• High-speed Scene Labeling on FPGA
• Learning Image Decompression with Convolutional Networks
• FPGA System Design for Computer Vision with Convolutional Neural Networks
• Change-based Evaluation of Convolutional Neural Networks
• PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB
• Implementing Hibernation on the ARM Cortex M0
• 3D Turbo Decoder ASIC Realization
• High-Throughput Hardware Implementations of Authenticated Encryption Algorithms
• ASIC Implementation of High-Throughput Next Generation Turbo Decoders
• Digital Transmitter for Mobile Communications
• FPGA-Based Digital Frontend for 3G Receivers
• Spatio-Temporal Video Filtering
• PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions
• FFT-based Convolutional Network Accelerator
• Real-Time Optical Flow Using Neural Networks
• Improving Scene Labeling with Hyperspectral Data
• Scattering Networks for Scene Labeling
• EvaLTE: A 2G/3G/4G Cellular Transceiver FMC
• Synchronisation and Cyclic Prefix Handling For LTE Testbed
• An FPGA-Based Testbed for 3G Mobile Communications Receivers
• Reading The GSM Beacon Carrier with OsmocomBB and stoneEDGE
• Baseband Meets CPU
• Active-Set QP Solver on FPGA
• Vector Processor for In-Memory Computing
• StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC
• Hardware/software co-programming on the Parallella platform
• EvalEDGE: A 2G Cellular Transceiver FMC
• A Trustworthy Three-Factor Authentication System
• RazorEDGE: An Evolved EDGE DBB ASIC
• Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA
• Time and Frequency Synchronization in LTE Cat-0 Devices
• Design and Implementation of ultra low power vision system
• Real-Time Stereo to Multiview Conversion
• Multiuser Equalization and Detection for 3GPP TD-SCDMA
• Design and Implementation of a Convolutional Neural Network Accelerator ASIC
• Design and Implementation of an Approximate Floating Point Unit
• Efficient Digital Signal Processing in High-Channel-Count High-Frame-Rate 3D Ultrasound Imaging Systems
• NORX - an AEAD algorithm for the CAESAR competition
• A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography
• Reconfigurability of SHA-3 candidates
• Data Mapping for Unreliable Memories
• Exploitation of Inherent Error Resilience of Wireless Systems under Unreliable Silicon
• High Throughput Turbo Decoder Design
• Turbo Decoder Design for High Code Rates
• Channel Decoding for TD-HSPA
• Near-Optimal Reduced-Complexity Sequence Detectors for TD-HSPA
• A Novel Constrained-Viterbi Algorithm with Linear Equalization and Grouping Assistance
• Successive Interference Cancellation for 3G Downlink
• Channel Estimation for TD-HSPA
• Evolved EDGE Physical Layer Incremental Redundancy Architecture
• MatPHY: An Open-Source Physical Layer Development Framework
• Interference Cancellation for Evolved EDGE on the RazorEDGE baseband ASIC
• Soft-Output Viterbi Equalizer as part of Evolved EDGE baseband ASIC
• Wireless Biomedical Signal Acquisition Device
• Flexible Front-End Circuit for Biomedical Data Acquisition
• High Performance Cellular Receivers in Very Advanced CMOS
• Multi-Band Receiver Design for LTE Mobile Communication
• High-Resolution, Calibrated Folding ADCs
• High-Resolution Large-Bandwidth Delta-Sigma A/D Converters in Ultra-Scaled CMOS
• SHAre - An application Specific Instruction Set Processor for SHA-2/3
• Compressed Sensing Reconstruction on FPGA
• Quantum Key Secured 100 Gbit/s Payload Encryption and its High-Speed Network Interfaces
• Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment
• A Multiview Synthesis Core in 65 nm CMOS
• Real-time View Synthesis using Image Domain Warping
• High-Throughput Authenticated Encryption Architectures based on Block Ciphers
• Putting Together What Fits Together - GrÆStl
• Ultra-low power processor design