Difference between revisions of "Category:Analog"
From iis-projects
| Line 1: | Line 1: | ||
| − | + | ==Analog and Mixed Signal Design Group== | |
| − | + | The analog and mixed signal design group lead by Prof. Qiuting Huang specializes in the analysis, design and optimization of state-of-the-art integrated circuits for a broad range of applications such as wireless and wireline communications, high speed computing, sensor interfaces and smart power. | |
<!-- | <!-- | ||
==Active Projects== | ==Active Projects== | ||
Revision as of 16:44, 30 January 2014
Contents
Analog and Mixed Signal Design Group
The analog and mixed signal design group lead by Prof. Qiuting Huang specializes in the analysis, design and optimization of state-of-the-art integrated circuits for a broad range of applications such as wireless and wireline communications, high speed computing, sensor interfaces and smart power.
Available Projects
We are still looking for students/partners to work on the following projects
- Digital Control of a DC/DC Buck Converter
- High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS
- High-Speed SAR ADC for next generation wireless communication in 12nm FinFET
- Analog building blocks for mmWave manipulation
- A mmWave Voltage-Controlled-Oscillator (VCO) for beyond 5G applications
- Bluetooth Low Energy network with optimized data throughput
- Event-Driven Convolutional Neural Network Modular Accelerator
- Level Crossing ADC For a Many Channels Neural Recording Interface
- 5G Cellular RF Front-end Design in 22nm CMOS Technology
- Design of Charge-Pump PLL in 22nm for 5G communication applications
Completed Projects
These are projects that were completed in the last few years
2013
- Wireless Biomedical Signal Acquisition Device
- Flexible Front-End Circuit for Biomedical Data Acquisition
- High-Resolution Large-Bandwidth Delta-Sigma A/D Converters in Ultra-Scaled CMOS
2012
- Data Mapping for Unreliable Memories
- Exploitation of Inherent Error Resilience of Wireless Systems under Unreliable Silicon
- High Throughput Turbo Decoder Design
- Turbo Decoder Design for High Code Rates
- Channel Decoding for TD-HSPA
- Near-Optimal Reduced-Complexity Sequence Detectors for TD-HSPA
- A Novel Constrained-Viterbi Algorithm with Linear Equalization and Grouping Assistance
- Successive Interference Cancellation for 3G Downlink
- Channel Estimation for TD-HSPA
- Evolved EDGE Physical Layer Incremental Redundancy Architecture
- MatPHY: An Open-Source Physical Layer Development Framework
- Interference Cancellation for Evolved EDGE on the RazorEDGE baseband ASIC
- Soft-Output Viterbi Equalizer as part of Evolved EDGE baseband ASIC
- High Performance Cellular Receivers in Very Advanced CMOS
- Multi-Band Receiver Design for LTE Mobile Communication
- High-Resolution, Calibrated Folding ADCs
Pages in category "Analog"
The following 73 pages are in this category, out of 73 total.
A
- A mmWave Voltage-Controlled-Oscillator (VCO) for beyond 5G applications
- A Novel Constrained-Viterbi Algorithm with Linear Equalization and Grouping Assistance
- Analog building blocks for mmWave manipulation
- Analog Layout Engine
- Analysis and Design of Power Efficient RF/ mm-Wave LC-tank Oscillator in 28nm for 5G communication applications
B
C
D
- Data Mapping for Unreliable Memories
- DC-DC Buck converter in 65nm CMOS
- Design of a 25 Gbps SerDes for optical chip-to-chip communication
- Design of a Digital Audio Module for Ultra-Low Power Cellular Applications
- Design of Charge-Pump PLL in 22nm for 5G communication applications
- Design of low-offset dynamic comparators
- Digital Control of a DC/DC Buck Converter
E
H
- Harald Kröll
- High Performance Cellular Receivers in Very Advanced CMOS
- High performance continous-time Delta-Sigma ADC for biomedical applications
- High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging
- High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT
- High Power Efficient Digitally Controlled Oscillator Design for Cellular IOT
- High Throughput Turbo Decoder Design
- High-Resolution Large-Bandwidth Delta-Sigma A/D Converters in Ultra-Scaled CMOS
- High-Resolution, Calibrated Folding ADCs
- High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS
- High-Speed SAR ADC for next generation wireless communication in 12nm FinFET
I
L
M
S
- Sandro Belfanti
- Soft-Output Viterbi Equalizer as part of Evolved EDGE baseband ASIC
- Stefan Lippuner
- Successive Approximation Register (SAR) ADC
- Successive Interference Cancellation for 3G Downlink
- User:Susman
- Switched Capacitor Based Bandgap-Reference
- Switched-capacitor power amplifier for IoT mobile communications: design of signal processing path
