Difference between revisions of "Category:Computer Architecture"
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Pages in category "Computer Architecture"
The following 119 pages are in this category, out of 119 total.
A
- A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)
- A Flexible Peripheral System for High-Performance Systems on Chip (M)
- A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B)
- A Snitch-based Compute Accelerator for HERO (M/1-2S)
- A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
- Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B)
- Adding Linux Support to our DMA Engine (1-2S/B)
- All the flavours of FFT on MemPool (1-2S/B)
- An Efficient Compiler Backend for Snitch (1S/B)
- An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
- Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Intregration
- Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Training Strategy And Algorithmic optimizations
- Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development
- Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
- AXI-based Network on Chip (NoC) system
B
C
- CLIC for the CVA6
- Coherence-Capable Write-Back L1 Data Cache for Ariane (M)
- Counter-based Fast Power Estimation using FPGAs (M/1-3S)
- Creating A Boundry Scan Generator (1-3S/B/2-3G)
- Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G)
- Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B)
- Creating a HDMI Video Interface for PULP
- Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B)
- Creating an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B)
- Cycle-Accurate Event-Based Simulation of Snitch Core
D
- Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B)
- Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M)
- Design of a Prototype Chip with Interleaved Memory and Network-on-Chip
- Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M)
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1-3S/B)
- Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems
- Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M)
- Developing a small portable neutron detector for detecting smuggled nuclear material
- Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B)
- Development of statistics and contention monitoring unit for PULP
- Digital
E
- Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M)
- Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
- Efficient Synchronization of Manycore Systems (M/1S)
- Enabling Efficient Systolic Execution on MemPool (M)
- Enhancing our DMA Engine with Fault Tolerance
- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
- Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B)
- Evaluating memory access pattern specializations in OoO, server-grade cores (M)
- Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M)
- Extend the RI5CY core with priviledge extensions
- Extended Verification for Ara
- Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)
- Extending our FPU with Internal High-Precision Accumulation (M)
- Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S)
- Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
F
I
- Ibex: Bit-Manipulation Extension
- Ibex: FPGA Optimizations
- Ibex: Tightly-Coupled Accelerators and ISA Extensions
- Implementation of a Coherent Application-Class Multicore System (1-2S)
- Implementation of a Heterogeneous System for Image Processing on an FPGA (S)
- Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
- Implementing Configurable Dual-Core Redundancy
- Implementing DSP Instructions in Banshee (1S)
- Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B)
- Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S)
- Integrating Hardware Accelerators into Snitch (1S)
- Investigating the Cost of Special-Case Handling in Low-Precision Floating-Point Dot Product Units (1S)
- Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
- IP-Based SoC Generation and Configuration (1-3S/B)
- ISA extensions in the Snitch Processor for Signal Processing (M)
L
M
N
O
P
R
S
T
- Taping a Safer Silicon Implementation of Snitch (M/2-3S)
- Timing Channel Mitigations for RISC-V Cores
- Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B)
- Towards a Technology-independent and Synthesizable AXI4 Performance Monitoring and Throttling Unit (1-2S)
- Towards Formal Verification of the iDMA Engine (1-3S/B)
- Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G)
- Trace Debugger for custom RISC-V Core
- Transforming MemPool into a CGRA (M)
- Triple-Core PULPissimo
