Category:Digital
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Pages in category "Digital"
The following 98 pages are in this category, out of 607 total.
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- Smart Virtual Memory Sharing
- Smart Wearable System For Vital Sign Monitoring Exploiting On Board and Cloud Machine Learning
- SmartRing
- Softmax for Transformers (M/1-2S)
- Spatio-Temporal Video Filtering
- Spatz grows wings: Physical Implementation of a Vector-Powered Manycore System (2S)
- Spiking Neural Network for Autonomous Navigation
- Spiking Neural Network for Motor Function Decoding Based on Neural Dust
- User:Sriedel
- Standard Cell Compatible Memory Array Design
- State-Saving @ NXP
- Stefan Lippuner
- Stefan Mach
- StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC
- Streaming Integer Extensions for Snitch (M/1-2S)
- Streaming Layer Normalization in ITA (M/1-2S)
- Study and Development of Intelligent Capability for Small-Size UAVs
- Sub Noise Floor Channel Estimation for the Cellular Internet of Things
- Subject specific embeddings for transfer learning in brain-computer interfaces
- User:Susman
- Synchronisation and Cyclic Prefix Handling For LTE Testbed
- System Analysis and VLSI Design of NB-IoT Baseband Processing
- System Emulation for AR and VR devices
T
- Taimir Aguacil
- Taping a Safer Silicon Implementation of Snitch (M/2-3S)
- TCNs vs. LSTMs for Embedded Platforms
- Ternary Neural Networks for Face Recognition
- Ternary Weights Engine For Efficient Many Channels Spike Sorting Applications
- Testbed Design for Self-sustainable IoT Sensors
- Thermal Control of Mobile Devices
- User:Thoriri
- Time and Frequency Synchronization in LTE Cat-0 Devices
- Time Gain Compensation for Ultrasound Imaging
- Time Synchronization for 3G Mobile Communications
- Timing Channel Mitigations for RISC-V Cores
- Tiny CNNs for Ultra-Efficient Object Detection on PULP
- Toward hyperdimensional active perception: learning compressed sensorimotor control by demonstration
- Toward Superposition of Brain-Computer Interface Models
- Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B)
- Towards a Technology-independent and Synthesizable AXI4 Performance Monitoring and Throttling Unit (1-2S)
- Towards Autonomous Navigation for Nano-Blimps
- Towards Flexible and Printable Wearables
- Towards Formal Verification of the iDMA Engine (1-3S/B)
- Towards global Brain-Computer Interfaces
- Towards Self Sustainable UAVs
- Towards Self-Sustainable Unmanned Aerial Vehicles
- Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G)
- Towards The Integration of E-skin into Prosthetic Devices
- Trace Debugger for custom RISC-V Core
- Training and Deploying Next-Generation Quantized Neural Networks on Microcontrollers
- Transformer Deployment on Heterogeneous Many-Core Systems
- Transforming MemPool into a CGRA (M)
- Triple-Core PULPissimo
- Turbo Equalization for Cellular IoT
U
- Ultra Low Power Conversion Circuit For Batteryless Applications
- Ultra Low Power Wake Up Radio for Wireless Sensor Network
- Ultra low power wearable ultrasound probe
- Ultra-Efficient Visual Classification on Movidius Myriad2
- Ultra-High-Efficiency Power Supply Management for Ultra-Low-Power Systems on Chip
- Ultra-low power processor design
- Ultra-wideband Concurrent Ranging
- Ultrafast Medical Ultrasound imaging on a GPU
- Ultrasound based hand gesture recognition
- Ultrasound Doppler system development
- Ultrasound High Speed Microbubble Tracking
- Ultrasound image data recycler
- Ultrasound Low power WiFi with IMX7
- Ultrasound measurement of microbubble stiffness for in situ detection of protease activity in clinical settings
- Ultrasound signal processing acceleration with CUDA
- Ultrasound-EMG combined hand gesture recognition
- Using Motion Sensors to Support Indoor Localization
V
- Variability Tolerant Ultra Low Power Cluster
- Variable Bit Precision Logic for Deep Learning and Artificial Intelligence
- Vector Processor for In-Memory Computing
- Vector-based Manycore HPC Cluster Exploration for 5G Communication Algorithm (1-2M)
- Vector-based Parallel Programming Optimization of Communication Algorithm (1-2S/B)
- Virtual Memory Ara
- Visualization of Neural Architecture Search Spaces
- Visualizing Functional Microbubbles using Ultrasound Imaging
- User:Vladn
- VLSI Implementation of a 5G Ciphering Accelerator
- VLSI Implementation of a Low-Complexity Channel Shortener for 2G EC-GSM-IoT and Evolved EDGE
- VLSI Implementation Polar Decoder using High Level Synthesis
W
- Wake Up Radio For Energy Efficient Communication System and IC Design
- Watchdog Timer for PULP
- WCDMA/HSPA+ Synchronization System Design, Implementation, and Testing
- Wearable Smart Camera With Deep Learning Algorithms For Automatic Detecion
- Wearable Ultrasound for Artery monitoring
- Wearables in Fashion
- Wiederverwendung (reuse) ganzer Funktionsblöcke beim VLSI-Entwurf
- Wireless Communication Systems for the IoT
- Wireless EEG Acquisition and Processing
- Wireless In Action Data Streaming in Ski Jumping (1 B/S)
- Wireless Sensing With Long Range Comminication (LoRa)
- Writing a Hero runtime for EPAC (1-3S/B)
