Category:Master Thesis
From iis-projects
The projects listed here are Master thesis projects. In principle a master project at IIS can take no longer than 6 months, and the student is expected to work full time on the thesis project. In some cases it is possible to make a simplified version of the project as a semester thesis, talk to the supervisor of the project to discuss this possibility.
Available Projects
- Short Range Radars For Biomedical Application
- Smart Patch For Heath Care And Rehabilitation
- Autonomus Drones With Novel Sensors And Ultra Wide Band
- Evaluating memory access pattern specializations in OoO, server-grade cores (M)
- Evaluating An Ultra low Power Vision Node
- Hypervisor Extension for Ariane (M)
- VLSI Implementation of a 5G Ciphering Accelerator
- Machine Learning on Ultrasound Images
- Outdoor Precision Object Tracking for Rockfall Experiments
- Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
- Coherence-Capable Write-Back L1 Data Cache for Ariane (M)
- Event-Driven Vision on an embedded platform
- Time Gain Compensation for Ultrasound Imaging
- Minimum Variance Beamforming for Wearable Ultrasound Probes
- Machine Learning for extracting Muscle features using Ultrasound
- Fluffy bunny project
- IBM Research
- Combining Spiking Neural Networks with Hyperdimensional Computing for Autonomous Navigation
- RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB
- Data Augmentation Techniques in Biosignal Classification
- Compression of iEEG Data
- BCI-controlled Drone
- Contrastive Learning for Self-supervised Clustering of iEEG Data for Epileptic Patients
- Real-Time Motor-Imagery Classification Using Neuromorphic Processor
- Palm size chip NMR probe
- MmWave PLL: 100GHz PLL using reference oversampling scheme
- Accurate deep learning inference using computational memory
- Spiking Neural Network for Autonomous Navigation
- Event-Driven Convolutional Neural Network Modular Accelerator
- Pressure and acoustic Smart Sensors Network for Wind Turbines Monitoring
- Characterization of the susceptibility to cosmic radiation of wide bandgap power devices by radioactive sources and at cryogenic temperatures
- Design of an on-field adaptable pulse-processing unit for semicondutor radiation detectors
- Design of an Ultra-Reliable Low-Latency Modem
- Towards global Brain-Computer Interfaces
- Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications
- Using piezoelectricity in monolayer 2D materials to build future nanoscale devices
- Source contact engineering in 2D materials MOSFET to achieve sub-60 mV/decade transistors
- Electrical characterization and optimization of electrochemical random-access memory for analog computing
- Finite element modeling of electrochemical random access memory
- Influence of the Initial Filament Geometry on the Forming Step in CBRAM.
- Nanoscale Hybrid III-V Plasmonic Laser for Low-Power Photonic ICs
- Design space exploration of InP Heterojunction Bipolar Transistors (DHBTs)
- Quantum transport in 2D heterostructures
- Design Of A Biomarker Assay Based On Responsive Magnetic Nanoparticles
- High-throughput Embedded System For Neurotechnology in collaboration with INI
- Neuromorphic Intelligence In An Embedded System in Collaboration with AiCTX
- Adversarial Attacks Against Deep Neural Networks In Wearable Cameras
- Wearable Smart Camera With Deep Learning Algorithms For Automatic Detecion
- Visualizing Functional Microbubbles using Ultrasound Imaging
- Energy Efficient Smart Devices For Construction Building Maintenance Hilti Collaboration
- Extending the RISCV backend of LLVM to support PULP Extensions
- Compiler Profiling and Optimizing
- PREM Intervals and Loop Tiling
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core
- Design and Exploitation of a Test-Bench for Non-Destructive Characterization of the Susceptibility of Silicon Carbide (SiC) Power Devices to Cosmic Radiation
- Experimental Validation of Impact Ionization Models for TCAD Simulation by a Novel Characterization Technique
- Design and implementation of the front-end for a portable ionizing radiation detector
- Level Crossing ADC For a Many Channels Neural Recording Interface
- Scalable Heterogeneous L1 Memory Interconnect for Smart Accelerator Coupling in Ultra-Low Power Multicores
- Improving Cold-Start in Batteryless And Energy Harvesting Systems
- SmartRing
- Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
- Optical Weights for Photonic Neural Networks
- Machine Learning-based Compressive Sensing Vehicle Location Tracking ASIC Design
- Digital Front End Design & Frequency Offset Estimation for V2X Communications
- High-Throughput Channel Coding & Decoding for V2X Communications
- High-Speed Channel Estimation & Tracking for V2X Communications
- Design of key building blocks for miniaturized sensor systems
- Energy Efficient Circuits for Wireless Neural Recording
- Application Specific Frequency Synthesizers (Analog/Digital PLLs)
- Edge Computing for Long-Term Wearable Biomedical Systems
- AMZ Driverless Competition Embedded Systems Projects
- Optogenetics And Game Theory Applied To Small Side Bird Using Smart Sensing
- Wireless Sensing With Long Range Comminication (LoRa)
- Indoor Smart Tracking of Hospital instrumentation
- A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications
- Physics is looking for PULP
- Embedded Gesture Recognition Using Novel Mini Radar Sensors
- Contextual Intelligence on Resource-constraint Bluetooth LE IoT Devices
- An Industrial-grade Bluetooth LE Mesh Network Solution
- Enabling Standalone Operation for a Mobile Health Platform
- Design and Implementation of a multi-mode multi-master I2C peripheral
- Ultra-low power transceiver for implantable devices
- OTDOA Positioning for LTE Cat-M
- Extend the RI5CY core with priviledge extensions
- BLISS - Battery-Less Identification System for Security
- Monocular Vision-based Object Following on Nano-size Robotic Blimp
- A Waypoint-based Navigation System for Nano-Size UAVs in GPS-denied Environments
- Zero Power Touch Sensor and Reciever For Body Communication
- Wake Up Radio For Energy Efficient Communication System and IC Design
- A Wireless Sensor Network for HPC monitoring
- High Speed FPGA Trigger Logic for Particle Physics Experiments
- Low Power One bit Microphone for Acoustic Imaging Using A Parallel Processor
- Low Power Geolocalization And Indoor Localization
- Inductive Charging Circuit for Implantable Devices
- Design of a 25 Gbps SerDes for optical chip-to-chip communication
- Neural Networks Framwork for Embedded Plattforms
- Hyper Meccano: Acceleration of Hyperdimensional Computing
- Autonomous Sensors For Underwater Monitoring In Smart Navy Systems
- Resilient Brain-Inspired Hyperdimensional Computing Architectures
- Variable Bit Precision Logic for Deep Learning and Artificial Intelligence
- Embedded Audio Source Localization Exploiting Coincidence Detection in Asynchronous Spike Streams
- Autoencoder Accelerator for On-Chip Semi-Supervised Learning
- 5G Cellular RF Front-end Design in 28nm CMOS Technology
- High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging
- Autonomous Sensing For Trains In The IoT Era
- VLSI Implementation Polar Decoder using High Level Synthesis
- Smart Wearable System For Vital Sign Monitoring Exploiting On Board and Cloud Machine Learning
- Convolution Neural Networks on our Ultra-Low Power Mult-Core Plattform PULP
- Single-Bit-Synapse Spiking Neural System-on-Chip
- Desing and Implementation Of Long Lasting Key Finder With Bleetooth Low Energy
- Radio Signal Direction Detection For Smart Glasses For Augmented Reality Applications
- Open Power-On Chip Controller Study and Integration
- Real-time eye movement analysis on a tablet computer
- Passive and Self Sustaining Receivers For On and Intra Body Communication For Wearable Sensors Networks
- A Wearable System To Control Phone And Electronic Device Without Hands
- Towards The Integration of E-skin into Prosthetic Devices
- Ultra Low Power Conversion Circuit For Batteryless Applications
- Towards Self Sustainable UAVs
- Fast Wakeup From Deep Sleep State
- Using Motion Sensors to Support Indoor Localization
- Low Power Neural Network For Multi Sensors Wearable Devices
- Bateryless Heart Rate Monitoring
- Birds Long Term Monitoring With Ultra Low Power Wireless Sensor Node
- Ultra-Efficient Visual Classification on Movidius Myriad2
- Kinetic Energy Harvesting For Autonomous Smart Watches
- A Wearable System for long term monitoring of human physiological parameters with E skin sensors
- Autonomous Smart Watches: Toward an ultra low power microphone detector with events classification
- Autonomous Smart Watches: Hardware and Software Desing
- A Wireless Sensor Network for a Smart LED Lighting control
- Compressed Sensing for Wireless Biosignal Monitoring
- Compressed Sensing vs JPEG
- Ultra-High-Efficiency Power Supply Management for Ultra-Low-Power Systems on Chip
- Real-Time Pedestrian Detection For Privacy Enhancement
- Thermal Control of Mobile Devices
- Android reliability governor
- Infrared Wake Up Radio
- Ambient RF Energy harvesting for Wireless Sensor Network
- ASIC Design of a Sigma Point Processor
- ASIC Design of a Gaussian Message Passing Processor
- Ab-initio modeling of ballistic thermal transport
- Development of an efficient algorithm for quantum transport codes
- Investigation of Metal Diffusion in Oxides for CBRAM Applications
- Ultra Low Power Wake Up Radio for Wireless Sensor Network
- Developing High Efficiency Batteries for Electric Cars
- Processing of 3D Micro-tomography data for Lithium Ion Batteries
Active Projects
- Next Generation Synchronization Signals
- Low Latency Brain-Machine Interfaces
- ISA extensions in the Snitch Processor for Signal Processing (M)
- PULP in space - Fault Tolerant PULP System for Critical Space Applications
- A Flexible Peripheral System for High-Performance Systems on Chip (M)
- Channel Estimation for 5G Cellular IoT and Fast Fading Channels
- Hyper-Dimensional Computing Based Predictive Maintenance
- Memory Augmented Neural Networks in Brain-Computer Interfaces
- Advanced 5G Repetition Combining
- An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications
Completed Projects
- NVDLA meets PULP
- Hardware Accelerators for Lossless Quantized Deep Neural Networks
- Energy-Efficient Brain-Inspired Hyperdimensional Computing
- Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development
- Floating-Point Divide & Square Root Unit for Transprecision
- TCNs vs. LSTMs for Embedded Platforms
- Timing Channel Mitigations for RISC-V Cores
- A computational memory unit using phase-change memory devices
- Real-Time Embedded Classification of Neural Activity in Rat Barrel Cortex
- Real-Time ECG Contractions Classification
- Exploring Algorithms for Early Seizure Detection
- Ternary Weights Engine For Efficient Many Channels Spike Sorting Applications
- Predictable Execution on GPU Caches
- CMOS power amplifier for field measurements in MRI systems
- Ultra-low power sampling front-end for acquisition of physiological signals
- Switched-capacitor power amplifier for IoT mobile communications: design of signal processing path
- Deep Learning for Brain-Computer Interface
- Digital Audio Interface for Smart Intensive Computing Triggering
- Trace Debugger for custom RISC-V Core
- Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration
- Turbo Equalization for Cellular IoT
- IoT Turbo Decoder
- BigPULP: Shared Virtual Memory Multicluster Extensions
- Sensor Fusion for Rockfall Sensor Node
- Intelligent Power Management Unit (iPMU)
- A Wireless Sensor Network for a Smart Building Monitor and Control
- Creating a HDMI Video Interface for PULP
- Standard Cell Compatible Memory Array Design
- A Wireless Sensor Network for HPC monitoring
- Study and Development of Intelligent Capability for Small-Size UAVs
- BigPULP: Multicluster Synchronization Extensions
- LTE-Advanced RF Front-end Design in 28nm CMOS Technology
- Switched Capacitor Based Bandgap-Reference
- Smart Virtual Memory Sharing
- Hardware Accelerated Derivative Pricing
- Glitches Reduce Listening Time of Your iPod
- Internet of Things Network Synchronizer
- Accelerator for Boosted Binary Features
- Accelerator for Spatio-Temporal Video Filtering
- High performance continous-time Delta-Sigma ADC for biomedical applications
- GUI-developement for an action-cam-based eye tracking device
- WCDMA/HSPA+ Synchronization System Design, Implementation, and Testing
- Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea
- Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors
- System Analysis and VLSI Design of NB-IoT Baseband Processing
- Learning Image Decompression with Convolutional Networks
- FPGA System Design for Computer Vision with Convolutional Neural Networks
- PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB
- 3D Turbo Decoder ASIC Realization
- ASIC Implementation of High-Throughput Next Generation Turbo Decoders
- FPGA-Based Digital Frontend for 3G Receivers
- Spatio-Temporal Video Filtering
- An FPGA-Based Testbed for 3G Mobile Communications Receivers
- Baseband Meets CPU
- Active-Set QP Solver on FPGA
- Vector Processor for In-Memory Computing
- Hardware/software co-programming on the Parallella platform
- Design and Implementation of ultra low power vision system
- Multiuser Equalization and Detection for 3GPP TD-SCDMA
- Efficient Digital Signal Processing in High-Channel-Count High-Frame-Rate 3D Ultrasound Imaging Systems
- Compressed Sensing Reconstruction on FPGA
- A Multiview Synthesis Core in 65 nm CMOS
- High-Throughput Authenticated Encryption Architectures based on Block Ciphers
- Putting Together What Fits Together - GrÆStl
Pages in category "Master Thesis"
The following 200 pages are in this category, out of 268 total.
(previous page) (next page)A
- A computational memory unit using phase-change memory devices
- A Flexible Peripheral System for High-Performance Systems on Chip (M)
- A Multiview Synthesis Core in 65 nm CMOS
- A Waypoint-based Navigation System for Nano-Size UAVs in GPS-denied Environments
- A Wearable System for long term monitoring of human physiological parameters with E skin sensors
- A Wearable System To Control Phone And Electronic Device Without Hands
- A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications
- A Wireless Sensor Network for a Smart Building Monitor and Control
- A Wireless Sensor Network for a Smart LED Lighting control
- A Wireless Sensor Network for HPC monitoring
- Ab-initio modeling of ballistic thermal transport
- Accelerator for Boosted Binary Features
- Accelerator for Spatio-Temporal Video Filtering
- Accurate deep learning inference using computational memory
- Active-Set QP Solver on FPGA
- Advanced 5G Repetition Combining
- Adversarial Attacks Against Deep Neural Networks In Wearable Cameras
- Ambient RF Energy harvesting for Wireless Sensor Network
- AMZ Driverless Competition Embedded Systems Projects
- An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications
- An FPGA-Based Testbed for 3G Mobile Communications Receivers
- An Industrial-grade Bluetooth LE Mesh Network Solution
- Android reliability governor
- Application Specific Frequency Synthesizers (Analog/Digital PLLs)
- Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development
- ASIC Design of a Gaussian Message Passing Processor
- ASIC Design of a Sigma Point Processor
- ASIC Development of 5G-NR LDPC Decoder
- ASIC Implementation of High-Throughput Next Generation Turbo Decoders
- Audio Video Preprocessing In Parallel Ultra Low Power Platform
- Autoencoder Accelerator for On-Chip Semi-Supervised Learning
- Autonomous Sensing For Trains In The IoT Era
- Autonomous Sensors For Underwater Monitoring In Smart Navy Systems
- Autonomous Smart Watches: Hardware and Software Desing
- Autonomous Smart Watches: Toward an ultra low power microphone detector with events classification
- Autonomus Drones With Novel Sensors And Ultra Wide Band
B
- Baseband Meets CPU
- Bateryless Heart Rate Monitoring
- BCI-controlled Drone
- BigPULP: Multicluster Synchronization Extensions
- BigPULP: Shared Virtual Memory Multicluster Extensions
- Biomedical Circuits, Systems, and Applications
- Birds Long Term Monitoring With Ultra Low Power Wireless Sensor Node
- BLISS - Battery-Less Identification System for Security
- Bringing XNOR-nets (ConvNets) to Silicon
C
- Cell Measurements for the 5G Internet of Things
- Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
- Channel Estimation and Equalization for LTE Advanced
- Channel Estimation for 5G Cellular IoT and Fast Fading Channels
- Characterization of the susceptibility to cosmic radiation of wide bandgap power devices by radioactive sources and at cryogenic temperatures
- CMOS power amplifier for field measurements in MRI systems
- Coherence-Capable Write-Back L1 Data Cache for Ariane (M)
- Combining Spiking Neural Networks with Hyperdimensional Computing for Autonomous Navigation
- Compiler Profiling and Optimizing
- Compressed Sensing for Wireless Biosignal Monitoring
- Compressed Sensing Reconstruction on FPGA
- Compressed Sensing vs JPEG
- Compression of iEEG Data
- Contextual Intelligence on Resource-constraint Bluetooth LE IoT Devices
- Contrastive Learning for Self-supervised Clustering of iEEG Data for Epileptic Patients
- Convolution Neural Networks on our Ultra-Low Power Mult-Core Plattform PULP
- CPS Software-Configurable State-Machine
- Creating a HDMI Video Interface for PULP
D
- DaCe on Snitch (M/1-3S)
- Data Augmentation Techniques in Biosignal Classification
- Deep Learning for Brain-Computer Interface
- Design and Exploitation of a Test-Bench for Non-Destructive Characterization of the Susceptibility of Silicon Carbide (SiC) Power Devices to Cosmic Radiation
- Design and Implementation of a multi-mode multi-master I2C peripheral
- Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors
- Design and implementation of the front-end for a portable ionizing radiation detector
- Design and Implementation of ultra low power vision system
- Design of a 25 Gbps SerDes for optical chip-to-chip communication
- Design Of A Biomarker Assay Based On Responsive Magnetic Nanoparticles
- Design of a Digital Audio Module for Ultra-Low Power Cellular Applications
- Design of a VLIW processor architecture based on RISC-V
- Design of an LTE Module for the Internet of Things
- Design of an on-field adaptable pulse-processing unit for semicondutor radiation detectors
- Design of an Ultra-Reliable Low-Latency Modem
- Design of key building blocks for miniaturized sensor systems
- Design of Scalable Event-driven Neural-Recording Digital Interface
- Design of State Retentive Flip-Flops
- Design space exploration of InP Heterojunction Bipolar Transistors (DHBTs)
- Desing and Implementation Of Long Lasting Key Finder With Bleetooth Low Energy
- Developing a small portable neutron detector for detecting smuggled nuclear material
- Developing High Efficiency Batteries for Electric Cars
- Development of an efficient algorithm for quantum transport codes
- Digital Audio Interface for Smart Intensive Computing Triggering
- Digital Front End Design & Frequency Offset Estimation for V2X Communications
- DMA Streaming Co-processor
E
- Edge Computing for Long-Term Wearable Biomedical Systems
- Efficient Implementation of an Active-Set QP Solver for FPGAs
- Electrical characterization and optimization of electrochemical random-access memory for analog computing
- Embedded Audio Source Localization Exploiting Coincidence Detection in Asynchronous Spike Streams
- Embedded Gesture Recognition Using Novel Mini Radar Sensors
- Enabling Standalone Operation for a Mobile Health Platform
- Energy Efficient Circuits for Wireless Neural Recording
- Energy Efficient Smart Devices For Construction Building Maintenance Hilti Collaboration
- Energy Neutral Multi Sensors Wearable Device
- Energy-Efficient Brain-Inspired Hyperdimensional Computing
- Evaluating An Ultra low Power Vision Node
- Evaluating memory access pattern specializations in OoO, server-grade cores (M)
- Evaluating the RiscV Architecture
- Event-Driven Convolutional Neural Network Modular Accelerator
- Event-Driven Vision on an embedded platform
- Experimental Validation of Impact Ionization Models for TCAD Simulation by a Novel Characterization Technique
- Exploring Algorithms for Early Seizure Detection
- Extend the RI5CY core with priviledge extensions
- Extending the RISCV backend of LLVM to support PULP Extensions
- Efficient Digital Signal Processing in High-Channel-Count High-Frame-Rate 3D Ultrasound Imaging Systems
F
- Fast Wakeup From Deep Sleep State
- Finite element modeling of electrochemical random access memory
- Floating-Point Divide & Square Root Unit for Transprecision
- Fluffy bunny project
- FPGA System Design for Computer Vision with Convolutional Neural Networks
- FPGA Testbed Implementation for Bluetooth Indoor Positioning
- FPGA-Based Digital Frontend for 3G Receivers
- FPGA-based Testbed Implementation of an Extended-Coverage Point-to-Point Communication Link for the Internet of Things
G
H
- Hardware Accelerated Derivative Pricing
- Hardware Accelerators for Lossless Quantized Deep Neural Networks
- Hardware/software co-programming on the Parallella platform
- High performance continous-time Delta-Sigma ADC for biomedical applications
- High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging
- High Speed FPGA Trigger Logic for Particle Physics Experiments
- High-Performance & V2X Cellular Communications
- High-Speed Channel Estimation & Tracking for V2X Communications
- High-Throughput Authenticated Encryption Architectures based on Block Ciphers
- High-Throughput Channel Coding & Decoding for V2X Communications
- High-throughput Embedded System For Neurotechnology in collaboration with INI
- Human Intranet
- Hyper Meccano: Acceleration of Hyperdimensional Computing
- Hyper-Dimensional Computing Based Predictive Maintenance
- Hypervisor Extension for Ariane (M)
I
- IBM Research
- Image and Video Processing
- Implementation of a NB-IoT Positioning System
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
- Improved Reacquisition for the 5G Cellular IoT
- Improving Cold-Start in Batteryless And Energy Harvesting Systems
- Indoor Smart Tracking of Hospital instrumentation
- Inductive Charging Circuit for Implantable Devices
- Influence of the Initial Filament Geometry on the Forming Step in CBRAM.
- Infrared Wake Up Radio
- Intelligent Power Management Unit (iPMU)
- Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea
- Internet of Things Network Synchronizer
- Investigation of Metal Diffusion in Oxides for CBRAM Applications
- IoT Turbo Decoder
- ISA extensions in the Snitch Processor for Signal Processing (M)
L
- LAPACK/BLAS for FPGA
- Learning Image Compression with Convolutional Networks
- Learning Image Decompression with Convolutional Networks
- Level Crossing ADC For a Many Channels Neural Recording Interface
- LightProbe
- LightProbe - CNN-Based-Image-Reconstruction
- Low Latency Brain-Machine Interfaces
- Low Power Geolocalization And Indoor Localization
- Low Power Neural Network For Multi Sensors Wearable Devices
- Low Power One bit Microphone for Acoustic Imaging Using A Parallel Processor
- Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration
- Low-power Clock Generation Solutions for 65nm Technology
- LTE IoT Network Synchronization
- LTE-Advanced RF Front-end Design in 28nm CMOS Technology
M
- Machine Learning for extracting Muscle features using Ultrasound
- Machine Learning on Ultrasound Images
- Machine Learning-based Compressive Sensing Vehicle Location Tracking ASIC Design
- Memory Augmented Neural Networks in Brain-Computer Interfaces
- Minimum Variance Beamforming for Wearable Ultrasound Probes
- MmWave PLL: 100GHz PLL using reference oversampling scheme
- Monocular Vision-based Object Following on Nano-size Robotic Blimp
- Multi issue OoO Ariane Backend (M)
- Multiuser Equalization and Detection for 3GPP TD-SCDMA
N
- Nanoscale Hybrid III-V Plasmonic Laser for Low-Power Photonic ICs
- Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications
- Neural Networks Framwork for Embedded Plattforms
- Neuromorphic Intelligence In An Embedded System in Collaboration with AiCTX
- Next Generation Channel Decoder
- Next Generation Synchronization Signals
- Non-binary LDPC Decoder for Deep-Space Optical Communications
- NVDLA meets PULP
O
- On-chip clock synthesizer design and porting
- Open Power-On Chip Controller Study and Integration
- Optical Weights for Photonic Neural Networks
- Optogenetics And Game Theory Applied To Small Side Bird Using Smart Sensing
- OTDOA Positioning for LTE Cat-M
- Outdoor Precision Object Tracking for Rockfall Experiments
P
- Palm size chip NMR probe
- Passive and Self Sustaining Receivers For On and Intra Body Communication For Wearable Sensors Networks
- Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
- Physics is looking for PULP
- Predictable Execution on GPU Caches
- PREM Intervals and Loop Tiling
- Pressure and acoustic Smart Sensors Network for Wind Turbines Monitoring
- Processing of 3D Micro-tomography data for Lithium Ion Batteries
- PULP in space - Fault Tolerant PULP System for Critical Space Applications