Category:Master Thesis
From iis-projects
The projects listed here are Master thesis projects. In principle a master project at IIS can take no longer than 6 months, and the student is expected to work full time on the thesis project. In some cases it is possible to make a simplified version of the project as a semester thesis, talk to the supervisor of the project to discuss this possibility.
Pages in category "Master Thesis"
The following 200 pages are in this category, out of 423 total.
(previous page) (next page)A
- A computational memory unit using phase-change memory devices
- A Flexible Peripheral System for High-Performance Systems on Chip (M)
- A FPGA-based data streaming system that enables real-time monitoring of cell culture and neuroactivities
- A mmWave Voltage-Controlled-Oscillator (VCO) for beyond 5G applications
- A Multiview Synthesis Core in 65 nm CMOS
- A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs
- A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
- A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S)
- A RISC-V ISA Extension for Scalar Chaining in Snitch (M)
- A Unified Compute Kernel Library for Snitch (1-2S)
- A Waypoint-based Navigation System for Nano-Size UAVs in GPS-denied Environments
- A Wearable System for long term monitoring of human physiological parameters with E skin sensors
- A Wearable System To Control Phone And Electronic Device Without Hands
- A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications
- A Wireless Sensor Network for a Smart Building Monitor and Control
- A Wireless Sensor Network for a Smart LED Lighting control
- A Wireless Sensor Network for HPC monitoring
- Accelerating Matrix Multiplication on a 216-core MPSoC (1M)
- Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B)
- Accelerator for Boosted Binary Features
- Accelerator for Spatio-Temporal Video Filtering
- Accurate deep learning inference using computational memory
- Active-Set QP Solver on FPGA
- Adaptively Controlled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B)
- Advanced 5G Repetition Combining
- Advanced EEG glasses
- Adversarial Attacks Against Deep Neural Networks In Wearable Cameras
- Ambient RF Energy harvesting for Wireless Sensor Network
- AMZ Driverless Competition Embedded Systems Projects
- An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications
- An Efficient Compiler Backend for Snitch (1S/B)
- An FPGA-Based Testbed for 3G Mobile Communications Receivers
- An Industrial-grade Bluetooth LE Mesh Network Solution
- An Ultra-Compact High-Power CMOS Power Amplifier for Millimeter-Wave 5G Communications
- An Ultra-Low-Power Neuromorphic Spiking Neuron Design
- Analog building blocks for mmWave manipulation
- Analog Compute-in-Memory Accelerator Interface and Integration
- Android reliability governor
- Application Specific Frequency Synthesizers (Analog/Digital PLLs)
- Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Intregration
- Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Training Strategy And Algorithmic optimizations
- Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development
- ASIC Design of a Gaussian Message Passing Processor
- ASIC Design of a Sigma Point Processor
- ASIC Development of 5G-NR LDPC Decoder
- ASIC Implementation of High-Throughput Next Generation Turbo Decoders
- ASR-Waveformer
- Audio Video Preprocessing In Parallel Ultra Low Power Platform
- Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
- Autoencoder Accelerator for On-Chip Semi-Supervised Learning
- Automatic unplugging detection for Ultrasound probes
- Autonomous Mapping with Nano-Drones UWB and Novel Depth Sensors
- Autonomous Obstacle Avoidance with Nano-Drones and Novel Depth Sensors
- Autonomous Sensing For Trains In The IoT Era
- Autonomous Sensors For Underwater Monitoring In Smart Navy Systems
- Autonomous Smart Watches: Hardware and Software Desing
- Autonomous Smart Watches: Toward an ultra low power microphone detector with events classification
- Autonomus Drones With Novel Sensors And Ultra Wide Band
- AXI-based Network on Chip (NoC) system
B
- Baseband Meets CPU
- Bateryless Heart Rate Monitoring
- Battery indifferent wearable Ultrasound
- BCI-controlled Drone
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- Benchmarking a RISC-V-based Server on LLMs/Foundation Models (SA or MA)
- BigPULP: Multicluster Synchronization Extensions
- BigPULP: Shared Virtual Memory Multicluster Extensions
- Biomedical Circuits, Systems, and Applications
- BirdGuard
- Birds Long Term Monitoring With Ultra Low Power Wireless Sensor Node
- BLISS - Battery-Less Identification System for Security
- Bridging QuantLab with LPDNN
- Bringing XNOR-nets (ConvNets) to Silicon
- Building an RTL top level for a Mempool-based Heterogeneous SoC (M/1-3S)
C
- Cell Measurements for the 5G Internet of Things
- Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
- Channel Estimation and Equalization for LTE Advanced
- Channel Estimation for 5G Cellular IoT and Fast Fading Channels
- Characterization of the susceptibility to cosmic radiation of wide bandgap power devices by radioactive sources and at cryogenic temperatures
- Characterization techniques for silicon photonics-Lumiphase
- Charge and heat transport through graphene nanoribbon based devices
- CLIC for the CVA6
- CMOS power amplifier for field measurements in MRI systems
- Coherence-Capable Write-Back L1 Data Cache for Ariane (M)
- Combining Multi Sensor Imaging and Machine Learning for Robust Far-Field Vision
- Combining Spiking Neural Networks with Hyperdimensional Computing for Autonomous Navigation
- Compiler Profiling and Optimizing
- Compressed Sensing for Wireless Biosignal Monitoring
- Compressed Sensing Reconstruction on FPGA
- Compressed Sensing vs JPEG
- Compression of Ultrasound data on FPGA
- Configurable Ultra Low Power LDO
- Contextual Intelligence on Resource-constraint Bluetooth LE IoT Devices
- Continual Learning for Adaptive EEG Monitoring in Epileptic Seizure Detection
- Contrastive Learning for Self-supervised Clustering of iEEG Data for Epileptic Patients
- Convolution Neural Networks on our Ultra-Low Power Mult-Core Plattform PULP
- Counter-based Fast Power Estimation using FPGAs (M/1-3S)
- CPS Software-Configurable State-Machine
- Creating a HDMI Video Interface for PULP
- Cycle-Accurate Event-Based Simulation of Snitch Core
D
- Data Augmentation Techniques in Biosignal Classification
- Deep Learning for Brain-Computer Interface
- Deep Learning-based Global Local Planner for Autonomous Nano-drones
- Design and Exploitation of a Test-Bench for Non-Destructive Characterization of the Susceptibility of Silicon Carbide (SiC) Power Devices to Cosmic Radiation
- Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors
- Design and implementation of the front-end for a portable ionizing radiation detector
- Design and Implementation of ultra low power vision system
- Design of a 25 Gbps SerDes for optical chip-to-chip communication
- Design Of A Biomarker Assay Based On Responsive Magnetic Nanoparticles
- Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M)
- Design of a Digital Audio Module for Ultra-Low Power Cellular Applications
- Design of a High-performance Hybrid PTZ for Multimodal Vision Systems
- Design of a Low Power Smart Sensing Multi-modal Vision Platform
- Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M)
- Design of a VLIW processor architecture based on RISC-V
- Design of an Area-Optimized Soft-Error Resilient Processing Core for Safety-Critical Systems (1M)
- Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems
- Design of an LTE Module for the Internet of Things
- Design of an on-field adaptable pulse-processing unit for semicondutor radiation detectors
- Design of combined Ultrasound and Electromyography systems
- Design of combined Ultrasound and PPG systems
- Design of low mismatch DAC used for VAD
- Design of MEMs Sensor Interface
- Design of Power-Noise-Efficient Discrete-Time Amplifier Using Open-Source Tools
- Design of Scalable Event-driven Neural-Recording Digital Interface
- Design of State Retentive Flip-Flops
- Design of Time-Encoded Spiking Neural Networks (IBM-Zurich)
- Design space exploration of InP Heterojunction Bipolar Transistors (DHBTs)
- Designing a Power Management Unit for PULP SoCs
- Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M)
- Desing and Implementation Of Long Lasting Key Finder With Bleetooth Low Energy
- Developing a small portable neutron detector for detecting smuggled nuclear material
- Developing High Efficiency Batteries for Electric Cars
- Development Of A Test Bed For Ultrasonic Transducer Characterization (1 S/B)
- Development of an efficient algorithm for quantum transport codes
- Development Of An FPGA-Based Optoacoustic Image Reconstruction Platform for Clinical Applications
- Development of an implantable Force sensor for orthopedic applications
- Development of statistics and contention monitoring unit for PULP
- Digital Audio Interface for Smart Intensive Computing Triggering
- DMA Streaming Co-processor
E
- Edge Computing for Long-Term Wearable Biomedical Systems
- EEG earbud
- EEG-based drowsiness detection
- Efficient Banded Matrix Multiplication for Quantum Transport Simulations
- Efficient collective communications in FlooNoC (1M)
- Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M)
- Efficient Implementation of an Active-Set QP Solver for FPGAs
- Efficient Synchronization of Manycore Systems (M/1S)
- Efficient TNN Inference on PULP Systems
- Electrically verifying a CMOS Multi-Modal Electrochemical, Impedance, and Optical Cellular Sensing Array for Massively Paralleled Exoelectrogen Screening
- Electrothermal characterization of van der Waals Heterostructures with a partial overlap
- Embedded Audio Source Localization Exploiting Coincidence Detection in Asynchronous Spike Streams
- Embedded Gesture Recognition Using Novel Mini Radar Sensors
- Enabling Efficient Systolic Execution on MemPool (M)
- Energy Efficient Serial Link
- Energy Efficient Smart Devices For Construction Building Maintenance Hilti Collaboration
- Energy Neutral Multi Sensors Wearable Device
- Energy-Efficient Brain-Inspired Hyperdimensional Computing
- Energy-efficient Circuits for Fully Wireless Brain-machine Interfaces
- Energy-Efficient Edge-Pursuit comparator for ultra-low power ADC
- Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B)
- Evaluating An Ultra low Power Vision Node
- Evaluating memory access pattern specializations in OoO, server-grade cores (M)
- Evaluating the RiscV Architecture
- Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M)
- Event-based navigation on autonomous nano-drones
- Event-Driven Convolutional Neural Network Modular Accelerator
- Event-Driven Vision on an embedded platform
- Every individual on the planet should have a real chance to obtain personalized medical therapy
- Experimental Validation of Impact Ionization Models for TCAD Simulation by a Novel Characterization Technique
- Exploring Algorithms for Early Seizure Detection
- Exploring NAS spaces with C-BRED
- Extend the RI5CY core with priviledge extensions
- Extending our FPU with Internal High-Precision Accumulation (M)
- Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S)
- Extending the RISCV backend of LLVM to support PULP Extensions
- Extreme-Edge Experience Replay for Keyword Spotting
- Efficient Digital Signal Processing in High-Channel-Count High-Frame-Rate 3D Ultrasound Imaging Systems
F
- Fast Accelerator Context Switch for PULP
- Fast Wakeup From Deep Sleep State
- Fault-Tolerant Floating-Point Units (M)
- Ferroelectric Memristors for Artificial Neural Networks (IBM-Zurich)
- Finite element modeling of electrochemical random access memory
- Flexfloat DL Training Framework
- Floating-Point Divide & Square Root Unit for Transprecision
- FPGA System Design for Computer Vision with Convolutional Neural Networks
- FPGA Testbed Implementation for Bluetooth Indoor Positioning
- FPGA-Based Digital Frontend for 3G Receivers
- FPGA-based Testbed Implementation of an Extended-Coverage Point-to-Point Communication Link for the Internet of Things
