Category:Semester Thesis

Semester thesis at the IIS is for 1-3 students for a duration of 14 weeks and should take 50% of the time of the students. The available projects in this category are meant primarily for a semester thesis. However if you are interested in the topic, you can discuss with the supervisor, in most cases the content of the project can be expanded to fit a master thesis as well.

Available Projects

• Online Learning of User Features (1S)
• Wearables in Fashion
• Efficient TNN Inference on PULP Systems
• Combining Multi Sensor Imaging and Machine Learning for Robust Far-Field Vision
• Implementing A Low-Power Sensor Node Network
• Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G)
• Physical Implementation of Ara, PULP's Vector Machine (1-2S)
• Manycore System on FPGA (M/S/G)
• Bluetooth Low Energy receiver in 65nm CMOS
• RVfplib
• Charge-Pump PLL with ring-oscillator based VCO in 65nm CMOS
• Bandgap voltage reference in 65nm CMOS
• DC-DC Buck converter in 65nm CMOS
• Low-Dropout Regulators for Magnetic Resonance Imaging
• Efficient Synchronization of Manycore Systems (M/1S)
• LED on Timer: On-chip Oscillator Tuned by Light to Compensate Temperature Variation
• Short Range Radars For Biomedical Application
• Smart Patch For Heath Care And Rehabilitation
• Autonomus Drones With Novel Sensors And Ultra Wide Band
• Evaluating An Ultra low Power Vision Node
• Hypervisor Extension for Ariane (M)
• Mapping Networks on Reconfigurable Binary Engine Accelerator
• Probabilistic training algorithms for quantized neural networks
• Exploring schedules for incremental and annealing quantization algorithms
• Machine Learning on Ultrasound Images
• IP-Based SoC Generation and Configuration (1-3S/B)
• Outdoor Precision Object Tracking for Rockfall Experiments
• Coherence-Capable Write-Back L1 Data Cache for Ariane (M)
• PREM Runtime Scheduling Policies
• Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
• Smart Meters
• Time Gain Compensation for Ultrasound Imaging
• Minimum Variance Beamforming for Wearable Ultrasound Probes
• Machine Learning for extracting Muscle features using Ultrasound
• Knowledge Distillation for Embedded Machine Learning
• Hardware Constrained Neural Architechture Search
• Fluffy bunny project
• IBM Research
• Combining Spiking Neural Networks with Hyperdimensional Computing for Autonomous Navigation
• Improved State Estimation on PULP-based Nano-UAVs
• Classification of Evoked Local-Field Potentials in Rat Barrel Cortex using Hyper-dimensional Computing
• Data Augmentation Techniques in Biosignal Classification
• Compression of iEEG Data
• BCI-controlled Drone
• Contrastive Learning for Self-supervised Clustering of iEEG Data for Epileptic Patients
• Nanoelectrode array biosensors - programmable non-overlapping clocks generator project
• Real-Time Motor-Imagery Classification Using Neuromorphic Processor
• Palm size chip NMR probe
• MmWave PLL: 100GHz PLL using reference oversampling scheme
• Deep neural networks for seizure detection
• Spiking Neural Network for Autonomous Navigation
• Event-Driven Convolutional Neural Network Modular Accelerator
• Pressure and acoustic Smart Sensors Network for Wind Turbines Monitoring
• Characterization of the susceptibility to cosmic radiation of wide bandgap power devices by radioactive sources and at cryogenic temperatures
• Design of an on-field adaptable pulse-processing unit for semicondutor radiation detectors
• Design of an Ultra-Reliable Low-Latency Modem
• Towards global Brain-Computer Interfaces
• Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications
• Design Of A Biomarker Assay Based On Responsive Magnetic Nanoparticles
• High-throughput Embedded System For Neurotechnology in collaboration with INI
• Neuromorphic Intelligence In An Embedded System in Collaboration with AiCTX
• Adversarial Attacks Against Deep Neural Networks In Wearable Cameras
• Wearable Smart Camera With Deep Learning Algorithms For Automatic Detecion
• Visualizing Functional Microbubbles using Ultrasound Imaging
• Energy Efficient Smart Devices For Construction Building Maintenance Hilti Collaboration
• Extending the RISCV backend of LLVM to support PULP Extensions
• Compiler Profiling and Optimizing
• PREM Intervals and Loop Tiling
• Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
• Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core
• Design and Exploitation of a Test-Bench for Non-Destructive Characterization of the Susceptibility of Silicon Carbide (SiC) Power Devices to Cosmic Radiation
• Experimental Validation of Impact Ionization Models for TCAD Simulation by a Novel Characterization Technique
• Design and implementation of the front-end for a portable ionizing radiation detector
• LightProbe - 200G Remote DMA for GPU FPGA Data Transfers
• Level Crossing ADC For a Many Channels Neural Recording Interface
• Scalable Heterogeneous L1 Memory Interconnect for Smart Accelerator Coupling in Ultra-Low Power Multicores
• Stand-Alone Edge Computing with GAP8
• Improving Cold-Start in Batteryless And Energy Harvesting Systems
• SmartRing
• Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
• Heart Rate Detection Algorithm
• Machine Learning-based Compressive Sensing Vehicle Location Tracking ASIC Design
• Digital Front End Design & Frequency Offset Estimation for V2X Communications
• High-Throughput Channel Coding & Decoding for V2X Communications
• High-Speed Channel Estimation & Tracking for V2X Communications
• PREM on PULP
• Design of key building blocks for miniaturized sensor systems
• Energy Efficient Circuits for Wireless Neural Recording
• Application Specific Frequency Synthesizers (Analog/Digital PLLs)
• Edge Computing for Long-Term Wearable Biomedical Systems
• AMZ Driverless Competition Embedded Systems Projects
• Optogenetics And Game Theory Applied To Small Side Bird Using Smart Sensing
• Wireless Sensing With Long Range Comminication (LoRa)
• Indoor Smart Tracking of Hospital instrumentation
• A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications
• Physics is looking for PULP
• Embedded Gesture Recognition Using Novel Mini Radar Sensors
• Contextual Intelligence on Resource-constraint Bluetooth LE IoT Devices
• An Industrial-grade Bluetooth LE Mesh Network Solution
• Enabling Standalone Operation for a Mobile Health Platform
• Design and Implementation of a multi-mode multi-master I2C peripheral
• Ultra-low power transceiver for implantable devices
• Optimal System Duty Cycling for a Mobile Health Platform
• Exploring Bio Impedance
• BLISS - Battery-Less Identification System for Security
• Monocular Vision-based Object Following on Nano-size Robotic Blimp
• Zero Power Touch Sensor and Reciever For Body Communication
• Wake Up Radio For Energy Efficient Communication System and IC Design
• A Wireless Sensor Network for HPC monitoring
• Low Power One bit Microphone for Acoustic Imaging Using A Parallel Processor
• Low Power Geolocalization And Indoor Localization
• Inductive Charging Circuit for Implantable Devices
• Design of a 25 Gbps SerDes for optical chip-to-chip communication
• Neural Networks Framwork for Embedded Plattforms
• Hyper Meccano: Acceleration of Hyperdimensional Computing
• Autonomous Sensors For Underwater Monitoring In Smart Navy Systems
• Resilient Brain-Inspired Hyperdimensional Computing Architectures
• Towards Online Training of CNNs: Hebbian-Based Deep Learning
• Embedded Audio Source Localization Exploiting Coincidence Detection in Asynchronous Spike Streams
• 5G Cellular RF Front-end Design in 28nm CMOS Technology
• Autonomous Sensing For Trains In The IoT Era
• Development of a syringe label reader for the neurocritical care unit
• Smart Wearable System For Vital Sign Monitoring Exploiting On Board and Cloud Machine Learning
• Tiny CNNs for Ultra-Efficient Object Detection on PULP
• OpenRISC SoC for Sensor Applications
• Design of Charge-Pump PLL in 28nm for 5G communication applications
• High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT
• High Power Efficient Digitally Controlled Oscillator Design for Cellular IOT
• Desing and Implementation Of Long Lasting Key Finder With Bleetooth Low Energy
• Radio Signal Direction Detection For Smart Glasses For Augmented Reality Applications
• PVT Dynamic Adaptation in PULPv3
• Linux Driver for fine-grain and low overhead access to on-chip performance counters
• Open Power-On Chip Controller Study and Integration
• Control an external ADC using Programmable Real-Time Unit (PRU) Subsystem on Beaglebone Black used as embedded HPC-performance-monitoring device
• Real-time eye movement analysis on a tablet computer
• Passive and Self Sustaining Receivers For On and Intra Body Communication For Wearable Sensors Networks
• A Wearable System To Control Phone And Electronic Device Without Hands
• Towards The Integration of E-skin into Prosthetic Devices
• Using Motion Sensors to Support Indoor Localization
• Low Power Neural Network For Multi Sensors Wearable Devices
• Birds Long Term Monitoring With Ultra Low Power Wireless Sensor Node
• Covariant Feature Detector on Parallel Ultra Low Power Architecture
• A Wearable System for long term monitoring of human physiological parameters with E skin sensors
• Autonomous Smart Watches: Toward an ultra low power microphone detector with events classification
• Autonomous Smart Watches: Hardware and Software Desing
• A Wireless Sensor Network for a Smart LED Lighting control
• Compressed Sensing vs JPEG
• Real-Time Pedestrian Detection For Privacy Enhancement
• Thermal Control of Mobile Devices
• Android reliability governor
• Infrared Wake Up Radio
• Ambient RF Energy harvesting for Wireless Sensor Network
• Hardware Support for IDE in Multicore Environment
• Investigation of Redox Processes in CBRAM
• Android Software Design
• Audio DAC Conversion Jitter Measurement System
• Hybrid Analog/Digital Leveling Loop for Very-Low-Distortion Oscillator
• Wiederverwendung (reuse) ganzer Funktionsblöcke beim VLSI-Entwurf
• Praxisgerechte Berechnung von Switching Noise in VLSI-Schaltungen
• Ultra Low Power Wake Up Radio for Wireless Sensor Network
• Assessment of novel photovoltaic architectures by circuit simulation
• Variability Tolerant Ultra Low Power Cluster

Active Projects

• Efficient TNN compression
• Event-Driven Vision on an embedded platform
• LLVM and DaCe for Snitch (1-2S)
• An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
• Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
• Multi issue OoO Ariane Backend (M)
• Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
• ASIC Development of 5G-NR LDPC Decoder
• Next Generation Synchronization Signals
• Low Latency Brain-Machine Interfaces
• PULP in space - Fault Tolerant PULP System for Critical Space Applications
• Channel Estimation for 5G Cellular IoT and Fast Fading Channels
• Hyper-Dimensional Computing Based Predictive Maintenance
• Memory Augmented Neural Networks in Brain-Computer Interfaces
• Advanced 5G Repetition Combining
• An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications
• Pulse Oximetry Fachpraktikum

Completed Projects

• Design and Evaluation of a Small Size Avalanche Beacon
• A Snitch-based Compute Accelerator for HERO (M/1-2S)
• MemPool on HERO (1S)
• Hardware Accelerators for Lossless Quantized Deep Neural Networks
• Energy-Efficient Brain-Inspired Hyperdimensional Computing
• A Recurrent Neural Network Speech Recognition Chip
• Implementation of a Heterogeneous System for Image Processing on an FPGA (S)
• Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development
• Deep Convolutional Autoencoder for iEEG Signals
• Ibex: FPGA Optimizations
• Ibex: Bit-Manipulation Extension
• Floating-Point Divide & Square Root Unit for Transprecision
• An Energy Efficient Brain-Computer Interface using Mr.Wolf
• Real-Time Embedded Classification of Neural Activity in Rat Barrel Cortex
• Real-Time ECG Contractions Classification
• Toward hyperdimensional active perception: learning compressed sensorimotor control by demonstration
• HERO: TLB Invalidation
• Indoor Positioning with Bluetooth
• Improving Resiliency of Hyperdimensional Computing
• Toward Superposition of Brain-Computer Interface Models
• Predictable Execution on GPU Caches
• Freedom from Interference in Heterogeneous COTS SoCs
• Analysis and Design of Power Efficient RF/ mm-Wave LC-tank Oscillator in 28nm for 5G communication applications
• Ultra-low power sampling front-end for acquisition of physiological signals
• Switched-capacitor power amplifier for IoT mobile communications: design of signal processing path
• Deep Learning for Brain-Computer Interface
• LightProbe - WIFI extension (PCB)
• Digital Audio Interface for Smart Intensive Computing Triggering
• Trace Debugger for custom RISC-V Core
• Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration
• Shared Correlation Accelerator for an RF SoC
• IoT Turbo Decoder
• Development of a Rockfall Sensor Node
• Intelligent Power Management Unit (iPMU)
• Ultrafast Medical Ultrasound imaging on a GPU
• LightProbe - Implementation of compressed-sensing algorithms
• A Wireless Sensor Network for a Smart Building Monitor and Control
• Creating a HDMI Video Interface for PULP
• Standard Cell Compatible Memory Array Design
• Efficient NB-IoT Uplink Design
• Interference Cancellation for EC-GSM-IoT
• A Wireless Sensor Network for HPC monitoring
• Linux Driver for built-in ADC using DMA and Programmable Real-Time Unit (PRU) support on Beaglebone Black used as embedded HPC-performance-monitoring device
• Signal-Processing and Data-Compression on Beaglebone Black used as embedded HPC-performance-monitoring device
• Towards Self-Sustainable Unmanned Aerial Vehicles
• Towards Autonomous Navigation for Nano-Blimps
• PULP-Shield for Autonomous UAV
• Self-Learning Drones based on Neural Networks
• BigPULP: Multicluster Synchronization Extensions
• LTE-Advanced RF Front-end Design in 28nm CMOS Technology
• Design of low-offset dynamic comparators
• VLSI Implementation of a Low-Complexity Channel Shortener for 2G EC-GSM-IoT and Evolved EDGE
• PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker
• Accelerator for Boosted Binary Features
• Accelerator for Spatio-Temporal Video Filtering
• Charging System for Implantable Electronics
• GUI-developement for an action-cam-based eye tracking device
• Ultra Low-Power Oscillator
• High-speed Scene Labeling on FPGA
• Learning Image Decompression with Convolutional Networks
• FPGA System Design for Computer Vision with Convolutional Neural Networks
• Change-based Evaluation of Convolutional Neural Networks
• Implementing Hibernation on the ARM Cortex M0
• 3D Turbo Decoder ASIC Realization
• High-Throughput Hardware Implementations of Authenticated Encryption Algorithms
• ASIC Implementation of High-Throughput Next Generation Turbo Decoders
• Digital Transmitter for Mobile Communications
• Spatio-Temporal Video Filtering
• PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions
• FFT-based Convolutional Network Accelerator
• Real-Time Optical Flow Using Neural Networks
• Improving Scene Labeling with Hyperspectral Data
• Scattering Networks for Scene Labeling
• Synchronisation and Cyclic Prefix Handling For LTE Testbed
• Reading The GSM Beacon Carrier with OsmocomBB and stoneEDGE
• Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA
• Time and Frequency Synchronization in LTE Cat-0 Devices
• Design and Implementation of ultra low power vision system
• Design and Implementation of a Convolutional Neural Network Accelerator ASIC
• Design and Implementation of an Approximate Floating Point Unit
• NORX - an AEAD algorithm for the CAESAR competition
• A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography
• Reconfigurability of SHA-3 candidates
• Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment
• Ultra-low power processor design