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We are listing a few projects below to give you an idea of what we do. However, we constantly have new project ideas and maybe some other approaches become obsolete in the very rapidly advancing research area. Please just contact the people of a project most similar to what you would like to do, and '''come talk to us'''.  
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==What is Deep Learning?==
 +
Nowadays, machine learning systems are the go-to choice when the cost of analytically deriving closed-form expressions to solve a given problem is prohibitive (e.g., it is very time-consuming, or the knowledge about the problem is insufficient). Machine learning systems can be particularly effective when the amount of data is large, since the statistics are expected to get more and more stable as the amount of data increases.
 +
Amongst machine learning systems, deep neural networks (DNNs) have established a reputation for their effectiveness and simplicity. To understand this success as compared to that of other machine learning systems, it is important to consider not only the accuracy performance of DNNs, but also their computational properties. The training algorithm (an iterative application of backpropagation and stochastic gradient descent) is linear in the data set size, making it more appealing in big data contexts than, for instance, support vector machines (SVMs). DNNs do not use branching instructions, making them predictable programs and allowing to design efficient access patterns for the memory hierarchies of the computing devices (exploiting spatial and temporal locality). DNNs are parallelizable, both at the neuron level and at the layer level. These predictability and parallelizability properties make DNNs an ideal fit for modern SIMD architectures and distributed computing systems.
 +
 
 +
 
 +
The main drawback of these systems is their size: millions or even billions of parameters are a common feature of many top-performing DNNs, and a proportional amount of arithmetic operations must be performed to process each data sample. Hence, to reduce the pressure of DNNs on the underlying computing infrastructure, research in computational deep learning has focussed on two families of optimizations: topological and hardware-oriented.
 +
'''Topological optimizations''' are concerned with network topologies (AKA network architectures) which are more efficient in terms of accuracy-per-parameter or accuracy-per-MAC (multiply-accumulate operation). As a specific form of topological optimization, '''pruning''' strategies aim at maximizing the number of zero-valued operands (parameters and/or activations) in order to 1) take advantage of sparsity (for storing the model) and to 2) minimize the number of effective arithmetic operations (i.e., the operations not involving zero-valued operands, which must be actually executed). '''Hardware-oriented optimizations''' are instead concerned with replacing time-consuming and energy-hungry operations, such as evaluations of transcendent functions or floating-point MAC operations, with more efficient counterparts, such as piecewise linear activation functions (e.g., the ReLU) and integer MAC operations (as in quantized neural networks, QNNs).
 +
 
 +
 
 +
==Foundation models and LLMs for Health==
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<!-- [[File:EEG_ECG.png|border|text-top|400px]] -->
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<!-- [[File:LLM.png|border|text-top|400px]] -->
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<!-- Seizure-prediction.png -->
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<!-- ==Short Description=== -->
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Incorporating Foundation Models and Large Language Models (LLMs) within artificial intelligence is gaining significant traction, particularly due to their potential applications in the health sector. This project is dedicated to developing sophisticated methodologies for utilizing foundation models and LLMs in health-related applications, specifically analyzing electroencephalogram (EEG) brain signals.
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 +
In healthcare and biomedical research, implementing advanced computational models, notably Foundation Models and Large Language Models (LLMs), revolutionizes the understanding and interpretation of intricate biosignals. We stand at the vanguard of this revolutionary change, delving into the capabilities of these models for the analysis and interpretation of critical biosignals, including electroencephalograms (EEG) and electrocardiograms (ECG).
 +
 
 +
Foundation Models, encompassing a spectrum of robust, pre-trained models, are transforming our ability to process and interpret large datasets. Initially trained on extensive and diverse datasets, these models are adaptable for specific tasks, offering remarkable accuracy and efficiency. This adaptability renders them particularly beneficial for biosignal analysis, where the intricacies of EEG and ECG data demand both precision and contextual understanding.
 +
 
 +
As a subset of Foundation Models, LLMs have demonstrated efficacy in processing and generating human language. At IIS, we are pioneering the application of LLMs in the domain of biosignal interpretation, extending beyond textual data. This entails training the models to interpret the 'language' of biosignals, translating complex patterns into actionable insights.
 +
 
 +
Our emphasis on EEG and ECG signals is motivated by these biosignals' profound insights into human health. EEGs, capturing brain activity, and ECGs, monitoring heart rhythms, are instrumental in diagnosing and managing various health conditions. By leveraging Foundation Models and LLMs, our objective is to refine diagnostic accuracy, predict health outcomes, and customize patient care.
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IIS invites Master's students to immerse themselves in this pioneering area. Our projects offer avenues to engage with state-of-the-art technologies, apply them to real-world health challenges, and contribute to shaping a future where healthcare is more predictive, preventive, and personalized. We encourage your participation in this exhilarating endeavor to redefine the confluence of healthcare and technology.
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 +
===Links===
 +
* [https://braingpt.org/ BrainGPT]
 +
 
 +
{|
 +
| style="padding: 10px" | [[File:philippmayer.jpg|frameless|left|100px]]
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|
 +
===[[:User:mayerph | Dr. Philipp Mayer]]===
 +
* '''e-mail''': [mailto:mayerph@iis.ee.ethz.ch mayerph@iis.ee.ethz.ch]
 +
* '''phone''': +41 44 63 242 68, '''skype''': mayer.philipp1
 +
* '''Office''': ETF F108
 +
|}
 +
 
 +
==Hardware-oriented neural architecture search (NAS)==
 +
The problems of topology selection and pruning can be considered instances of the classical statistics problems of model selection and feature selection, respectively. In the scope of deep learning, model selection is also called neural architecture search (NAS).
 +
When designing a DNN topology, you have a large number of degrees of freedom at your disposal: number of layers, number of neurons for each layer, connectivity of each neuron, and so on; moreover, the number of choices for each degree of freedom is huge. These properties imply that the design space for a DNN can grow exponentially, making exhaustive searches prohibitive. Therefore, to increase the efficiency of the exploration, stochastic optimization tools are the preferred choice: evolutionary algorithms, reinforcement learning, gradient-based techniques or even random graph generation.
 +
An interesting feature of model selection is that specific constraints can be enforced on the search space so that desired properties are always respected. For instance, given a storage budget describing a hard limitation of the chosen computing platform, the network generation algorithm can be limited to propose topologies that do not exceed a given number of parameters. This capability of incorporating HW features as constraints on the search space make NAS algorithms very interesting in the context of generating HW-friendly DNNs.
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 +
{|
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| style="padding: 10px" | [[File:Thorir.jpg|frameless|left|96px]]
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|
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===[[:User:Thoriri| Thorir Mar Ingolfsson]]===
 +
* '''e-mail''': [mailto:thoriri@iis.ee.ethz.ch thoriri@iis.ee.ethz.ch]
 +
* '''phone''': +41 44 633 88 43
 +
* '''office''': ETZ J76.2
 +
|}
 +
 
 +
{|
 +
| style="padding: 10px" | [[File:Cioflanc.jpg|frameless|left|96px]]
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|
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===[[:User:Cioflanc| Cristian Cioflan]]===
 +
* '''e-mail''': [mailto:cioflanc@iis.ee.ethz.ch cioflanc@iis.ee.ethz.ch]
 +
* '''phone''':  +41 44 632 67 89
 +
* '''office''': ETZ J89
 +
|}
 +
 
 +
{|
 +
| style="padding: 10px" | [[File:victor_jung.jpg|frameless|left|96px]]
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|
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===[[:User:Jungvi| Victor Jung]]===
 +
* '''e-mail''': [mailto:jungvi@iis.ee.ethz.ch jungvi@iis.ee.ethz.ch]
 +
* '''phone''':  TBD
 +
* '''office''': ETZ J69.2
 +
|}
 +
 
 +
==Algorithms & Frameworks for Quantization and Deployment for Deep Neural Networks (DNNs)==
 +
The typical training algorithm for DNNs is an iterative application of the backpropagation algorithm (BP) and stochastic gradient descent (SGD).
 +
When the quantization is not “aggressive” (i.e., when the parameters and feature maps can be represented as integers with a precision of 8-bits or more), many solutions are available either in specialized literature or in commercial software that can convert models pre-trained with gradient descent to quantized counterparts (post-training quantization).
 +
But when the precision is extremely reduced (i.e., 1-bit or 2-bits operands), these solutions can no longer be applied, and quantization-aware training algorithms are needed. The naive application of gradient descent (which in theory is not even correct) to train these QNNs yields major accuracy drops. Hence, it is likely that suitable training algorithms for QNNs require to replace the standard BP+SGD scheme, which is suitable for differentiable optimization, with search strategies that are more apt for discrete optimization.
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{|
 +
| style="padding: 10px" | [[File:victor_jung.jpg|frameless|left|96px]]
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|
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===[[:User:Jungvi| Victor Jung]]===
 +
* '''e-mail''': [mailto:jungvi@iis.ee.ethz.ch jungvi@iis.ee.ethz.ch]
 +
* '''phone''':  TBD
 +
* '''office''': ETZ J69.2
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|}
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 +
{|
 +
| style="padding: 10px" | [[File:Cioflanc.jpg|frameless|left|96px]]
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|
 +
===[[:User:Cioflanc| Cristian Cioflan]]===
 +
* '''e-mail''': [mailto:cioflanc@iis.ee.ethz.ch cioflanc@iis.ee.ethz.ch]
 +
* '''phone''':  +41 44 632 67 89
 +
* '''office''': ETZ J89
 +
|}
 +
 
 +
{|
 +
| style="padding: 10px" | [[File:Georg.jpg|frameless|left|96px]]
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|
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===[[User:Georg | Georg Rutishauser]]===
 +
* '''e-mail''': [mailto:georgr@iis.ee.ethz.ch georgr@iis.ee.ethz.ch]
 +
* '''phone''': +41 44 632 54 97
 +
* '''office''': ETZ J68.2
 +
|}
 +
 
 +
{|
 +
| style="padding: 10px" | [[File:Wiesep.jpg|frameless|left|96px]]
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|
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===[[User:Wiesep | Philip Wiese]]===
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* '''e-mail''': [mailto:wiesep@iis.ee.ethz.ch wiesep@iis.ee.ethz.ch]
 +
* '''phone''': +41 79 244 92 40
 +
* '''office''': OAT U25
 +
|}
 +
 
 +
==Hardware Acceleration of DNNs and QNNs==
 +
Deep Learning (DL) and Artificial Intelligence (AI) are quickly becoming dominant paradigms for all kinds of analytics, complementing or replacing traditional data science methods. Successful at-scale deployment of these algorithms requires deploying them directly at the data source, i.e. in the IoT end-nodes collecting data. However, due to the extreme constraints of these devices (in terms of power, memory footprint, area cost), performing full DL inference in-situ in low-power end-nodes requires a breakthrough in computational performance and efficiency.
 +
It is widely known that the numerical representation typically used when developing DL algorithms (single-precision floating-point) encodes a higher precision than what is actually required to achieve high quality-of-results in inference (Courbariaux et al. 2016); this fact can be exploited in the design of energy-efficient hardware for DL.
 +
For example, by using ternary weights, which means all network weights are quantized to {-1,0,1}, we can design the fundamental compute units in hardware without using an HW-expensive multiplication unit. Additionally, it allows us to store the weights much more compact on-chip.
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{|
 +
| style="padding: 10px" | [[File:angelo_garofalo.png|frameless|left|96px]]
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|
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===[[:User:Agarofalo| Angelo Garofalo]]===
 +
* '''e-mail''': [mailto:agarofalo@iis.ee.ethz.ch agarofalo@iis.ee.ethz.ch]
 +
* '''phone''': +41 44 632 82 19
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* '''office''': ETZ J78
 +
|}
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{|
 +
| style="padding: 10px" | [[File:Georg.jpg|frameless|left|96px]]
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|
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===[[User:Georg | Georg Rutishauser]]===
 +
* '''e-mail''': [mailto:georgr@iis.ee.ethz.ch georgr@iis.ee.ethz.ch]
 +
* '''phone''': +41 44 632 54 97
 +
* '''office''': ETZ J68.2
 +
|}
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{|
 +
| style="padding: 10px" | [[File:Moritz_scherer.jpg|frameless|left|96px]]
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|
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===[[:User:Scheremo| Moritz Scherer]]===
 +
* '''e-mail''': [mailto:scheremo@iis.ee.ethz.ch scheremo@iis.ee.ethz.ch]
 +
* '''phone''': +41 44 632 77 86
 +
* '''office''': ETZ J69.2
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|}
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 +
{|
 +
| style="padding: 10px" | [[File:Arpan_Suravi_Prasad.jpeg|frameless|left|96px]]
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|
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 +
===[[:User:Prasadar| Arpan Suravi Prasad]]===
 +
* '''e-mail''': [mailto:prasadar@iis.ee.ethz.ch prasadar@iis.ee.ethz.ch]
 +
* '''phone''': +41 44 632 44 91
 +
* '''office''': ETZ J89
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|}
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 +
{|
 +
| style="padding: 10px" | [[File:gislamoglu.jpg|frameless|left|96px]]
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|
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===[[:User:Gislamoglu| Gamze İslamoğlu]]===
 +
* '''e-mail''': [mailto:gislamoglu@iis.ee.ethz.ch gislamoglu@iis.ee.ethz.ch]
 +
* '''office''': ETZ J78
 +
|}
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 +
{|
 +
| style="padding: 10px" | [[File:Wiesep.jpg|frameless|left|96px]]
 +
|
 +
===[[User:Wiesep | Philip Wiese]]===
 +
* '''e-mail''': [mailto:wiesep@iis.ee.ethz.ch wiesep@iis.ee.ethz.ch]
 +
* '''phone''': +41 79 244 92 40
 +
* '''office''': OAT U25
 +
|}
 +
 
 +
==Event-Driven Computing==
 +
With the increasing demand for "smart" algorithms on mobile and wearable devices, the energy cost of computing is becoming the bottleneck for battery lifetime. One approach to defuse this bottleneck is to reduce the compute activity on such devices - one of the most popular approaches uses sensor information to determine whether it is worth to run expensive computations or whether there is not enough activity in the environment. This approach is called event-driven computing.
 +
Event-driven architectures can be implemented for many applications - From pure sensing platforms to multi-core systems for machine learning on the edge.
 +
At IIS, we cover most of these applications. Besides working with novel, state-of-the-art sensors and sensing platforms to push the limits of lifetime of wearables and mobile devices, we also work with cutting-edge computing systems like Intel Loihi for Spiking Neural Networks to minimize the energy cost of machine intelligence.
 +
 
 +
{|
 +
| style="padding: 10px" | [[File:Adimauro.png|frameless|left|96px]]
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|
 +
===[[:User:Adimauro| Alfio Di Mauro]]===
 +
* '''e-mail''': [mailto:adimauro@iis.ee.ethz.ch adimauro@iis.ee.ethz.ch]
 +
* '''phone''': +41 44 632 82 19
 +
* '''office''': ETZ J78
 +
|}
 +
{|
 +
| style="padding: 10px" | [[File:Moritz_scherer.jpg|frameless|left|96px]]
 +
|
 +
===[[:User:Scheremo| Moritz Scherer]]===
 +
* '''e-mail''': [mailto:scheremo@iis.ee.ethz.ch scheremo@iis.ee.ethz.ch]
 +
* '''phone''': +41 44 632 77 86
 +
* '''office''': ETZ J69.2
 +
|}
 +
{|
 +
| style="padding: 10px" | [[File:Arpan_Suravi_Prasad.jpeg|frameless|left|96px]]
 +
|
 +
 
 +
===[[:User:Prasadar| Arpan Suravi Prasad]]===
 +
* '''e-mail''': [mailto:prasadar@iis.ee.ethz.ch prasadar@iis.ee.ethz.ch]
 +
* '''phone''': +41 44 632 44 91
 +
* '''office''': ETZ J89
 +
|}
 +
 
 +
 
 +
==On-Device Training==
 +
 
 +
The fast development of the Internet-of Things (IoT) comes with the growing need for smart end-node devices able to execute Deep Learning networks locally. Processing the data on device has many advantages, not only drastically reducing the latency and communication energy cost, but also taking one step towards autonomous IoT end-nodes. Most of the current research efforts are focusing on inference, under the "train-then-deploy" paradigm. However, this results in a device unable to face real-life phenomena such as data distribution shifts or class increments. At IIS, we are actively researching new methods to tackle this significant challenge in the context of tightly memory constrained devices such as Microcontrollers (MCUs).
 +
 
 +
 
 +
{|
 +
| style="padding: 10px" | [[File:Cioflanc.jpg|frameless|left|96px]]
 +
|
 +
===[[:User:Cioflanc| Cristian Cioflan]]===
 +
* '''e-mail''': [mailto:cioflanc@iis.ee.ethz.ch cioflanc@iis.ee.ethz.ch]
 +
* '''phone''':  +41 44 632 67 89
 +
* '''office''': ETZ J89
 +
|}
 +
 
 +
{|
 +
| style="padding: 10px" | [[File:viviane_potocnik.png|frameless|left|96px]]
 +
|
 +
===[[:User:Vivianep| Viviane Potocnik]]===
 +
* '''e-mail''': [mailto:vivianep@iis.ee.ethz.ch vivianep@iis.ee.ethz.ch]
 +
* '''phone''':  TBD
 +
* '''office''': ETZ J78
 +
|}
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 +
{|
 +
| style="padding: 10px" | [[File:victor_jung.jpg|frameless|left|96px]]
 +
|
 +
===[[:User:Jungvi| Victor Jung]]===
 +
* '''e-mail''': [mailto:jungvi@iis.ee.ethz.ch jungvi@iis.ee.ethz.ch]
 +
* '''phone''':  TBD
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* '''office''': ETZ J69.2
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|}
  
 
==Prerequisites==
 
==Prerequisites==
We have no strict, general requirements, as they are highly dependent on the exact project steps. The projects will be adapted to the skills and interests of the student(s) -- just come talk to us! If you don't know about GPU programming or CNNs or ... just let us know and we can together determine what is a useful way to go -- after all you are here to learn not only about project work, but also to develop your technical skills.  
+
We have no strict, general requirements, as they are highly dependent on the exact project steps. The projects will be adapted to the skills and interests of the student(s) -- just come talk to us! If you don't know about GPU programming or CNNs or ... just let us know and we can together determine what is a useful way to go -- after all you are here to learn not only about project work but also to develop your technical skills.
  
Only hard requirements:  
+
Only hard requirements:
* Excitement for deep learning  
+
* '''Excitement for deep learning'''
* For VLSI projects: VLSI 1 or equivalent
+
* For '''HW Design''' projects: '''VLSI 1, VLSI 2''' or equivalent
 +
 
 +
==Tags==
 +
All our projects will be categorized into three categories. Therefore, look out for the following tags:
 +
* '''Algorithmic''' -  you will mainly make algorithmic evaluations using languages and frameworks like e.g. Python, Pytorch, Tensorflow and our in-house frameworks like Quantlab, DORY, NEMO
 +
* '''Embedded Coding''' - you will implement e.g. c-code for one of our microcontrollers
 +
* '''HW Design''' - you will be designing HW including writing RTL, simulate, synthesize, and layout (backend) some HW
  
 
<!--- <span style="color:red">We are currently out of working spaces at IIS until around Easter 2018. Please contact us 1-2 months before the desired project start!</span> --->
 
<!--- <span style="color:red">We are currently out of working spaces at IIS until around Easter 2018. Please contact us 1-2 months before the desired project start!</span> --->
  
==Projects==
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==Available Projects==
{| class="wikitable"
+
New projects are constantly being added, check back often! If you have any questions or would like to propose own ideas, do not hesitate to contact us!
|-
+
<DynamicPageList>
! Status !! Type !! Project Name !! Description !! Platform !! Workload Type !! First Contact(s)
+
category = Available
|-
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category = Digital
| taken || SA || CBinfer for Speech Recognition || We have recently published an approach to dramatically reduce computation effort when performing object detection on video streams with limited frame-to-frame changes (cf. [https://arxiv.org/pdf/1704.04313.pdf paper]). We think this approach could also be applied to audio signals for continuous listening to void commands: when looking at MFCCs or the short-term Fourier transform, changes in the spectrum between neighboring time windows are also limited. || Embedded GPU (Tegra X2) || SW (GPU, algo evals) || [[:User:lukasc|Lukas Cavigelli]]
+
category = Deep Learning Projects
|-
+
suppresserrors=true
<!--- | CBinfer+ || Running CNNs to a large extent means a tremendous computational effort, particularly when looking at object detection and image segmentation. For many applications we want to run everything in real-time on video data. We exploit that only few pixels change from frame to frame (cf. [https://arxiv.org/pdf/1704.04313.pdf paper]). We have several ideas on a) how to improve the algorithm, and b) would like to optimize the implementation for the next generation of (embedded) GPUs. You can be part of this (already successful) research path. || Embedded GPU (Tegra X2) || SW (GPU, algo evals) || [[:User:lukasc|Lukas Cavigelli]]
+
ordermethod=sortkey
|-
+
order=ascending
--->
+
</DynamicPageList>
<!---
+
<DynamicPageList>
| available || CBinfer HW  || MA/2x SA|| The motiviation here is the same as for CBinfer+. Here we want to build a custom hardware architecture for ASICs capable of running this type of workload. || ASIC || HW (ASIC) || [[:User:lukasc|Lukas Cavigelli]]
+
category = Available
|-
+
category = Digital
--->
+
category = Event-Driven Computing
| taken || MA || One-shot/Few-shot Learning || One-shot learning comes in handy whenever it is not possible to collect a large dataset. Consider for example face identification as a form of opening you apartment's door, where the user provides a single picture (not 100s) and is recognized reliably from then on. In this project you would apply a method called Prototypical Networks (cf. [[https://arxiv.org/abs/1703.05175 paper], [https://github.com/jakesnell/prototypical-networks code]]) to learn to identify faces. Once you have trained such a DNN, you will optimize it for an embedded system to run it in real time. For a master thesis, an interesting additional step could be to look at expanding this further to share information between multiple nodes/cameras and learn to re-identify faces also as they evolve over time. || Embedded GPU or Microcontroller || SW (algo, uC) || [[:User:lukasc|Lukas Cavigelli]], [[:User:andrire|Renzo Andri]]
+
suppresserrors=true
|-
+
</DynamicPageList>
| taken || MA/2x SA || DNN Training Accelerator || The compute effort to train state-of-the-art CNNs is tremendous and largely done on GPUs, or less frequently on specialized HW (e.g. Google's TPUs). Their energy effiency and often performance is limited by DRAM accesses. When storing all the data required for the gradient descent step of typical DNNs, there is no way to store it in on-chip SRAM--even across multiple, very large chips. Recently, Invertible ResNets has been presented (cf. [https://arxiv.org/pdf/1707.04585.pdf paper]) and allows to trade these storage requirements for some more compute effort--a huge opportunity. In this project, you will perform an architecture exploration to analyze how this could best be exploited. || ASIC || HW (ASIC) || [[:User:lukasc|Lukas Cavigelli]]
 
|-
 
| available || MA || INQ Accelerator || INQ is a quantization technique which has been proven to work very well for neural networks. The weights are quantized to levels of +-2^n. As multiplcations with power's of two can be done by just shifting the bits, it is perfect for HW acceleration. In this thesis you will design an ASIC performing INQ quantized networks. || ASIC || ASIC || [[:User:andrire|Renzo Andri]]
 
|-
 
| available || MA || Distributed/Federated Learning || With the increasing number of IoT devices equipped with a bunch of sensor, it is not feasible to always stream all the data back to a server. Therefore, there is the need to learn on the node itself and synchronize/merge the network in a periodic scheme. || Embedded GPU || SW(algo, evals) || [[:User:andrire|Renzo Andri]], [[:User:lukasc|Lukas Cavigelli]]
 
|-
 
| available || MA/SA || Self-Learning Drone || Autonomous Driving is a hot topic nowadays, but also self-learning approaches (i.e. re-inforcement learning) have had a big success (e.g. AlphaGo from Google beat the world champion in Go. We want a drone to learn from its environment such that the drone is able to solve a task independantly. || ML frameworks (e.g. Torch)/GPU, Drone Simulation (ROS/Gazebo) || SW (Training) || [[:User:andrire|Renzo Andri]], [[:User:dpalossi|Daniele Palossi]]
 
|-
 
| available || MA/SA || On-chip Learning || Neural Networks are compute and resource intensive and are usually run on power-intensive GPU clusters, but we would like to exploit them also on the everywhere IoT devices. To reach that, we need to develop new hardware architecture optimized for this application. This also include to check new algorithmic approach, which can reduce the compute or memory footprint of these networks. || ASIC || HW (ASIC) || [[:User:andrire|Renzo Andri]]
 
|-
 
| available || SA || SAR Data Analysis || We would like to explore the automated analysis of aerial synthetic aperture radar (SAR) images. Essentially, we have one very high-resolution image of a Swiss city and no labels. This project is not about labeling a lot of data, but to explore various options for supervised (cf. [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7827114 paper]) or semi-/unsupervised learning to segment these images using very few labeled data. || Workstation|| SW (algo evals) || [[:User:xiaywang|Xiaying Wang]], [[:User:lukasc|Lukas Cavigelli]], [[:User:magnom|Michele Magno]]
 
|-
 
| available || SA/MA || Weather Invariant Representations || When running computer vision applications, their performance under lab conditions often significantly differs from what you using real-world data. One main aspect is that often lighting conditions are normalized. Your target is to train a CNN to normalize weather conditions and going through the entire flow of collecting a dataset, training a CNN, and evaluating it. This type of problem can likely be approach with unsupervised or semi-supervised methods. || Workstation|| SW (algo evals, data acq.) || [[:User:lukasc|Lukas Cavigelli]]
 
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Workload types: SW (GPU), SW (microcontr.), SW (algorithm evals), HW (FPGA), HW (ASIC), HW (PCB)
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==Projects in Progress==
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[[:User:andrire|Renzo Andri]], ETZ J 76.2, andrire@iis.ee.ethz.ch<br />
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[[:User:lukasc|Lukas Cavigelli]], ETZ J 76.2, cavigelli@iis.ee.ethz.ch
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Latest revision as of 18:29, 19 February 2024

What is Deep Learning?

Nowadays, machine learning systems are the go-to choice when the cost of analytically deriving closed-form expressions to solve a given problem is prohibitive (e.g., it is very time-consuming, or the knowledge about the problem is insufficient). Machine learning systems can be particularly effective when the amount of data is large, since the statistics are expected to get more and more stable as the amount of data increases. Amongst machine learning systems, deep neural networks (DNNs) have established a reputation for their effectiveness and simplicity. To understand this success as compared to that of other machine learning systems, it is important to consider not only the accuracy performance of DNNs, but also their computational properties. The training algorithm (an iterative application of backpropagation and stochastic gradient descent) is linear in the data set size, making it more appealing in big data contexts than, for instance, support vector machines (SVMs). DNNs do not use branching instructions, making them predictable programs and allowing to design efficient access patterns for the memory hierarchies of the computing devices (exploiting spatial and temporal locality). DNNs are parallelizable, both at the neuron level and at the layer level. These predictability and parallelizability properties make DNNs an ideal fit for modern SIMD architectures and distributed computing systems.


The main drawback of these systems is their size: millions or even billions of parameters are a common feature of many top-performing DNNs, and a proportional amount of arithmetic operations must be performed to process each data sample. Hence, to reduce the pressure of DNNs on the underlying computing infrastructure, research in computational deep learning has focussed on two families of optimizations: topological and hardware-oriented. Topological optimizations are concerned with network topologies (AKA network architectures) which are more efficient in terms of accuracy-per-parameter or accuracy-per-MAC (multiply-accumulate operation). As a specific form of topological optimization, pruning strategies aim at maximizing the number of zero-valued operands (parameters and/or activations) in order to 1) take advantage of sparsity (for storing the model) and to 2) minimize the number of effective arithmetic operations (i.e., the operations not involving zero-valued operands, which must be actually executed). Hardware-oriented optimizations are instead concerned with replacing time-consuming and energy-hungry operations, such as evaluations of transcendent functions or floating-point MAC operations, with more efficient counterparts, such as piecewise linear activation functions (e.g., the ReLU) and integer MAC operations (as in quantized neural networks, QNNs).


Foundation models and LLMs for Health

Incorporating Foundation Models and Large Language Models (LLMs) within artificial intelligence is gaining significant traction, particularly due to their potential applications in the health sector. This project is dedicated to developing sophisticated methodologies for utilizing foundation models and LLMs in health-related applications, specifically analyzing electroencephalogram (EEG) brain signals.

In healthcare and biomedical research, implementing advanced computational models, notably Foundation Models and Large Language Models (LLMs), revolutionizes the understanding and interpretation of intricate biosignals. We stand at the vanguard of this revolutionary change, delving into the capabilities of these models for the analysis and interpretation of critical biosignals, including electroencephalograms (EEG) and electrocardiograms (ECG).

Foundation Models, encompassing a spectrum of robust, pre-trained models, are transforming our ability to process and interpret large datasets. Initially trained on extensive and diverse datasets, these models are adaptable for specific tasks, offering remarkable accuracy and efficiency. This adaptability renders them particularly beneficial for biosignal analysis, where the intricacies of EEG and ECG data demand both precision and contextual understanding.

As a subset of Foundation Models, LLMs have demonstrated efficacy in processing and generating human language. At IIS, we are pioneering the application of LLMs in the domain of biosignal interpretation, extending beyond textual data. This entails training the models to interpret the 'language' of biosignals, translating complex patterns into actionable insights.

Our emphasis on EEG and ECG signals is motivated by these biosignals' profound insights into human health. EEGs, capturing brain activity, and ECGs, monitoring heart rhythms, are instrumental in diagnosing and managing various health conditions. By leveraging Foundation Models and LLMs, our objective is to refine diagnostic accuracy, predict health outcomes, and customize patient care.

IIS invites Master's students to immerse themselves in this pioneering area. Our projects offer avenues to engage with state-of-the-art technologies, apply them to real-world health challenges, and contribute to shaping a future where healthcare is more predictive, preventive, and personalized. We encourage your participation in this exhilarating endeavor to redefine the confluence of healthcare and technology.

Links

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Dr. Philipp Mayer

Hardware-oriented neural architecture search (NAS)

The problems of topology selection and pruning can be considered instances of the classical statistics problems of model selection and feature selection, respectively. In the scope of deep learning, model selection is also called neural architecture search (NAS). When designing a DNN topology, you have a large number of degrees of freedom at your disposal: number of layers, number of neurons for each layer, connectivity of each neuron, and so on; moreover, the number of choices for each degree of freedom is huge. These properties imply that the design space for a DNN can grow exponentially, making exhaustive searches prohibitive. Therefore, to increase the efficiency of the exploration, stochastic optimization tools are the preferred choice: evolutionary algorithms, reinforcement learning, gradient-based techniques or even random graph generation. An interesting feature of model selection is that specific constraints can be enforced on the search space so that desired properties are always respected. For instance, given a storage budget describing a hard limitation of the chosen computing platform, the network generation algorithm can be limited to propose topologies that do not exceed a given number of parameters. This capability of incorporating HW features as constraints on the search space make NAS algorithms very interesting in the context of generating HW-friendly DNNs.

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Thorir Mar Ingolfsson

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Cristian Cioflan

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Victor Jung

Algorithms & Frameworks for Quantization and Deployment for Deep Neural Networks (DNNs)

The typical training algorithm for DNNs is an iterative application of the backpropagation algorithm (BP) and stochastic gradient descent (SGD). When the quantization is not “aggressive” (i.e., when the parameters and feature maps can be represented as integers with a precision of 8-bits or more), many solutions are available either in specialized literature or in commercial software that can convert models pre-trained with gradient descent to quantized counterparts (post-training quantization). But when the precision is extremely reduced (i.e., 1-bit or 2-bits operands), these solutions can no longer be applied, and quantization-aware training algorithms are needed. The naive application of gradient descent (which in theory is not even correct) to train these QNNs yields major accuracy drops. Hence, it is likely that suitable training algorithms for QNNs require to replace the standard BP+SGD scheme, which is suitable for differentiable optimization, with search strategies that are more apt for discrete optimization.

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Victor Jung

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Cristian Cioflan

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Georg Rutishauser

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Philip Wiese

Hardware Acceleration of DNNs and QNNs

Deep Learning (DL) and Artificial Intelligence (AI) are quickly becoming dominant paradigms for all kinds of analytics, complementing or replacing traditional data science methods. Successful at-scale deployment of these algorithms requires deploying them directly at the data source, i.e. in the IoT end-nodes collecting data. However, due to the extreme constraints of these devices (in terms of power, memory footprint, area cost), performing full DL inference in-situ in low-power end-nodes requires a breakthrough in computational performance and efficiency. It is widely known that the numerical representation typically used when developing DL algorithms (single-precision floating-point) encodes a higher precision than what is actually required to achieve high quality-of-results in inference (Courbariaux et al. 2016); this fact can be exploited in the design of energy-efficient hardware for DL. For example, by using ternary weights, which means all network weights are quantized to {-1,0,1}, we can design the fundamental compute units in hardware without using an HW-expensive multiplication unit. Additionally, it allows us to store the weights much more compact on-chip.


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Angelo Garofalo

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Georg Rutishauser

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Moritz Scherer

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Arpan Suravi Prasad

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Gamze İslamoğlu

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Philip Wiese

Event-Driven Computing

With the increasing demand for "smart" algorithms on mobile and wearable devices, the energy cost of computing is becoming the bottleneck for battery lifetime. One approach to defuse this bottleneck is to reduce the compute activity on such devices - one of the most popular approaches uses sensor information to determine whether it is worth to run expensive computations or whether there is not enough activity in the environment. This approach is called event-driven computing. Event-driven architectures can be implemented for many applications - From pure sensing platforms to multi-core systems for machine learning on the edge. At IIS, we cover most of these applications. Besides working with novel, state-of-the-art sensors and sensing platforms to push the limits of lifetime of wearables and mobile devices, we also work with cutting-edge computing systems like Intel Loihi for Spiking Neural Networks to minimize the energy cost of machine intelligence.

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Alfio Di Mauro

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Moritz Scherer

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Arpan Suravi Prasad


On-Device Training

The fast development of the Internet-of Things (IoT) comes with the growing need for smart end-node devices able to execute Deep Learning networks locally. Processing the data on device has many advantages, not only drastically reducing the latency and communication energy cost, but also taking one step towards autonomous IoT end-nodes. Most of the current research efforts are focusing on inference, under the "train-then-deploy" paradigm. However, this results in a device unable to face real-life phenomena such as data distribution shifts or class increments. At IIS, we are actively researching new methods to tackle this significant challenge in the context of tightly memory constrained devices such as Microcontrollers (MCUs).


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Cristian Cioflan

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Viviane Potocnik

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Victor Jung

Prerequisites

We have no strict, general requirements, as they are highly dependent on the exact project steps. The projects will be adapted to the skills and interests of the student(s) -- just come talk to us! If you don't know about GPU programming or CNNs or ... just let us know and we can together determine what is a useful way to go -- after all you are here to learn not only about project work but also to develop your technical skills.

Only hard requirements:

  • Excitement for deep learning
  • For HW Design projects: VLSI 1, VLSI 2 or equivalent

Tags

All our projects will be categorized into three categories. Therefore, look out for the following tags:

  • Algorithmic - you will mainly make algorithmic evaluations using languages and frameworks like e.g. Python, Pytorch, Tensorflow and our in-house frameworks like Quantlab, DORY, NEMO
  • Embedded Coding - you will implement e.g. c-code for one of our microcontrollers
  • HW Design - you will be designing HW including writing RTL, simulate, synthesize, and layout (backend) some HW


Available Projects

New projects are constantly being added, check back often! If you have any questions or would like to propose own ideas, do not hesitate to contact us!


Projects in Progress


Completed Projects