Information for "Design and Implementation of a Convolutional Neural Network Accelerator ASIC"
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Basic information
| Display title | Design and Implementation of a Convolutional Neural Network Accelerator ASIC |
| Default sort key | Design and Implementation of a Convolutional Neural Network Accelerator ASIC |
| Page length (in bytes) | 9,080 |
| Page ID | 284 |
| Page content language | English (en) |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 1 |
| Counted as a content page | Yes |
Page protection
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
Edit history
| Page creator | Lukasc (talk | contribs) |
| Date of page creation | 19:04, 6 December 2014 |
| Latest editor | Lukasc (talk | contribs) |
| Date of latest edit | 19:45, 24 March 2015 |
| Total number of edits | 48 |
| Total number of distinct authors | 1 |
| Recent number of edits (within past 90 days) | 0 |
| Recent number of distinct authors | 0 |
