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Difference between revisions of "Design and Implementation of a multi-mode multi-master I2C peripheral"

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[[Category:Analog]]
 
[[Category:Semester Thesis]]
 
[[Category:Semester Thesis]]
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[[Category:Master Thesis]]
 
[[Category:Available]]
 
[[Category:Available]]
 
[[Category:Glaserf]]
 
[[Category:Glaserf]]
[[Category:Brunn]]
 
 
[[Category:PULP]]
 
[[Category:PULP]]
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[[Category:Software]]
 
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[[Category:Processor]]
[[Category:Biomedical Systems on Chip]]
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[[Category:Biomedical System on Chips]]

Revision as of 18:20, 13 September 2019

Even though introduced more than 35 years ago, the two-wire Inter-Integrated Circuit bus I2C is still widely used in modern electronics. Our biomedical platform is no exception to this; low-speed communication between the three programmable chips is enabled through I2C. One optional feature of the I2C protocol is that connected nodes may dynamically switch roles from master to slave and back during operation, similarly multiple masters may coexist and arbitrate the bus control within each other.

So far, this feature is only available in the commercial RF-SoC and not in the chips that we designed ourselves, rendering many low-level system management jobs challenging and cumbersome. In this project, you will extend the existing I2C-module that connects to an energy-efficient and powerful peripheral DMA with multi-master and slave capabilities. An important part of the work is the verification of the module under various usage scenarios where other masters and slaves will be present.

Status: Available

We are looking for 1-2 motivated Semester Thesis students
Contact: Florian Glaser

Prerequisites

  • Some experience with hardware design (VHDL/(System-)Verilog), for example completion of VLSI I lecture
  • Interest in embedded bus systems

Character

  • 20% Concept
  • 60% Hardware Design (in System Verilog)
  • 20% Verification/Experiments