Design and VLSI Implementation of a Constrained-Viterbi Algorithm for 3GPP TD-HSPA
From iis-projects
Revision as of 09:52, 17 March 2015 by Weberbe (talk | contribs) (Weberbe moved page Design and VLSI Implementation of a Constrained-Viterbi Algorithm for 3GPP TD-HSPA to Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA: real title)
Redirect page