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Design of a 25 Gbps SerDes for optical chip-to-chip communication

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Short Description

While the computing capacity of modern systems has been doubling every 13 months, the I/O bandwidth of microprocessors and memory has doubled only every 30 months, becoming the bottleneck of high performance computers.

This limitation is coming from RF attenuation, which imposes hard trade-offs between data-rate, power dissipation and reach distance. Moving the chip to chip communication on the optical domain can bypass those issues, allowing power efficient and high transmission rates.

The proposed project targets the realization of a 25 Gbps serializer/deserializer that will be fabricated in a 45 nm CMOS SOI. Together with the optical modulator and demodulator realized on the same chip, it will demonstrate the first 25 Gbps optical link in a zero-change CMOS technology.

Status: Available

Looking for 1 Master or semester student
Contact: Mattia, Thomas Burger

Prerequisites

AIC

Character

20% Theory
80% Circuit Design

Professor

Qiuting Huang

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Detailed Task Description

Goals

Practical Details

Results

Links

  1. Single-chip microprocessor that communicates directly using light

C Sun, MT Wade, Y Lee, JS Orcutt, L Alloatti… - Nature, 2015↑ top