Difference between revisions of "Design of a VLIW processor architecture based on RISC-V"
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[[Category:Digital]] [[Category:Master Thesis
[[Category:Digital]] [[Category:Master Thesis]] [[Category:2016]] [[Category:ASIC]] [[Category:PULP]] [[Category:Processor]]
Latest revision as of 09:25, 5 November 2019
RISC-V is an open source instruction set architecture (ISA) designed by UC Berkeley. For the PULP architecture we have designed our own RISC-V cores which target maximum energy efficiency. The cores are based on an in-order, 4 stage 32b pipeline. However, RISC-V is not only proposing 32b instructions, but also 16b(so-called compressed instructions), 48b, and 64b instructions. Our core is already supporting 16b, and 32b instructions, but as we have single-issue, in-order pipeline, the cores can only execute one instruction at the time. Moving to a very long instruction word (VLIW) architecture has several interesting advantages. Assuming a e.g. 48b instruction interface, the core would have the possibility to fetch 2 instructions (1*32b+1*16b) which can then be processed in parallel. (e.g. 1 ALU + 1 LSU instruction)
Throughout this project, your main task will be to come up with a good micro-architecture to minimize the overheads of the wider instruction interface and write simple C-applications in order to show the increased speed of the VLIW-architecture.
The tasks of this project are rather challenging as the VLSI architecture of a VLIW processor is by far more complex than that of a RISC architecture. We therefore recommend it to a more experienced student. (master project)
- Supervisors: Michael Gautschi
- VLSI I
- Interest and good knowledge in Computer Architectures (RISC, VLIW architectures)
- VHDL/System Verilog knowledge
- programming in C
- 40% Theory
- 35% ASIC Design
- 25% Verification