Difference between revisions of "Design of an Ultra-Reliable Low-Latency Modem"
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Currently avalaible Projects: | Currently avalaible Projects: | ||
| − | * | + | * Currently no specific projects are advertised. Contact us if you're interested in a project in the field. |
| − | |||
| − | |||
===Status: Available === | ===Status: Available === | ||
| − | : Looking for Semester/Master students | + | : Looking for Bachelor/Semester/Master students |
: Contact: [[:User:Lstefan | Stefan Lippuner]] | : Contact: [[:User:Lstefan | Stefan Lippuner]] | ||
===Prerequisites=== | ===Prerequisites=== | ||
: An interest in wireless communication and signal processing | : An interest in wireless communication and signal processing | ||
: Matlab programming experience is helpful | : Matlab programming experience is helpful | ||
| + | |||
<!-- | <!-- | ||
===Status: Completed === | ===Status: Completed === | ||
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: 50% VHDL implementation | : 50% VHDL implementation | ||
: 30% FPGA testing / ASIC design (optional) | : 30% FPGA testing / ASIC design (optional) | ||
| + | |||
| + | == Previous Projects == | ||
| + | |||
| + | === Projects in Progress === | ||
| + | * MIMO processing: Investigate the requirements for URLLC MIMO processing. Run simulations and implement your algorithm in hardware. | ||
| + | * 5G NR LDPC Decoder | ||
| + | * 5G NR Polar Decoder | ||
| + | * [[VLSI Implementation of a 5G Ciphering Accelerator]]< | ||
| + | |||
| + | === Completed Projects === | ||
| + | * 5G URLLC Matlab Simulation Framework | ||
| + | * VHDL Design of a Symbol Detector for 5G Cellular URLLC | ||
| + | * 5G URLLC FPGA Testbed and Synchronization | ||
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---> | ---> | ||
== Related Projects== | == Related Projects== | ||
| − | [[ | + | [[Wireless Communication Systems for the IoT]] |
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[[Category:Digital]] | [[Category:Digital]] | ||
[[Category:FPGA]] | [[Category:FPGA]] | ||
| + | [[Category:ASIC]] | ||
[[Category:Telecommunications]] | [[Category:Telecommunications]] | ||
[[Category:Available]] | [[Category:Available]] | ||
| + | [[Category:Bachelor Thesis]] | ||
[[Category:Semester Thesis]] | [[Category:Semester Thesis]] | ||
[[Category:Master Thesis]] | [[Category:Master Thesis]] | ||
Revision as of 16:51, 22 December 2020
Contents
Introduction
Applications like factory automation, remote surgery, or vehicle control require extremely low latency connections, which also have to be very reliable at the same time. So far this has only been possible using wired connections, but the Ultra-Reliable Low-Latency Communication (URLLC) extension to 5G aims to provide a wireless option. The goals include 99.999% reliability and 1 ms end-to-end latency at the same time. This only leaves about 70-140 μs for the entire digital signal processing, compared to 4000 μs in LTE.
Project Description
We're currently building a FPGA-based testbed for 5G URLLC. During a typical project you can implement a key building block for the system.
Currently avalaible Projects:
- Currently no specific projects are advertised. Contact us if you're interested in a project in the field.
Status: Available
- Looking for Bachelor/Semester/Master students
- Contact: Stefan Lippuner
Prerequisites
- An interest in wireless communication and signal processing
- Matlab programming experience is helpful
Character (depends on the project)
- 20% Theory, Algorithms and Simulation
- 50% VHDL implementation
- 30% FPGA testing / ASIC design (optional)
Previous Projects
Projects in Progress
- MIMO processing: Investigate the requirements for URLLC MIMO processing. Run simulations and implement your algorithm in hardware.
- 5G NR LDPC Decoder
- 5G NR Polar Decoder
- VLSI Implementation of a 5G Ciphering Accelerator<
Completed Projects
- 5G URLLC Matlab Simulation Framework
- VHDL Design of a Symbol Detector for 5G Cellular URLLC
- 5G URLLC FPGA Testbed and Synchronization
Professor
Related Projects
Wireless Communication Systems for the IoT
https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8486954
