Difference between revisions of "Design of an Ultra-Reliable Low-Latency Modem"
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* Come up with a low-latency architecture for the processing of the equalized symbols: Selection, demapping, descrambling and accumulation. After that you will implement your hardware accelerator and verify that it works correctly. | * Come up with a low-latency architecture for the processing of the equalized symbols: Selection, demapping, descrambling and accumulation. After that you will implement your hardware accelerator and verify that it works correctly. | ||
* MIMO processing: Investigate the requirements for URLLC MIMO processing. Run simulations and implement your algorithm in hardware. | * MIMO processing: Investigate the requirements for URLLC MIMO processing. Run simulations and implement your algorithm in hardware. | ||
Revision as of 14:05, 4 May 2020
Contents
Introduction
Applications like factory automation, remote surgery, or vehicle control require extremely low latency connections, which also have to be very reliable at the same time. So far this has only been possible using wired connections, but the Ultra-Reliable Low-Latency Communication (URLLC) extension to 5G aims to provide a wireless option. The goals include 99.999% reliability and 1 ms end-to-end latency at the same time. This only leaves about 70-140 μs for the entire digital signal processing, compared to 4000 μs in LTE.
Project Description
We're currently building a FPGA-based testbed for 5G URLLC. During a typical project you can implement a key building block for the system.
Currently avalaible Projects:
- Come up with a low-latency architecture for the processing of the equalized symbols: Selection, demapping, descrambling and accumulation. After that you will implement your hardware accelerator and verify that it works correctly.
- MIMO processing: Investigate the requirements for URLLC MIMO processing. Run simulations and implement your algorithm in hardware.
Status: Available
- Looking for Semester/Master students
- Contact: Stefan Lippuner
Prerequisites
- An interest in wireless communication and signal processing
- Matlab programming experience is helpful
Character (depends on the project)
- 20% Theory, Algorithms and Simulation
- 50% VHDL implementation
- 30% FPGA testing / ASIC design (optional)
Professor
Related Projects
RF SoCs for the Internet of Things
https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8486954
