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Revision as of 14:01, 5 February 2016
Projects that are part of the Digital Circuits and Systems group
Contents
Available Projects
We are still looking for students/partners to work on the following projects
HOT Topics
- Efficient Synchronization of Manycore Systems (M/1S)
- An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
- Evaluating An Ultra low Power Vision Node
- Probabilistic training algorithms for quantized neural networks
- Exploring schedules for incremental and annealing quantization algorithms
- VLSI Implementation of a 5G Ciphering Accelerator
- Efficient TNN compression
- Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
- Event-Driven Vision on an embedded platform
- Knowledge Distillation for Embedded Machine Learning
- Hardware Constrained Neural Architechture Search
- IBM Research
- Combining Spiking Neural Networks with Hyperdimensional Computing for Autonomous Navigation
- RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB
- Improved State Estimation on PULP-based Nano-UAVs
- Data Augmentation Techniques in Biosignal Classification
- Compression of iEEG Data
- BCI-controlled Drone
- Contrastive Learning for Self-supervised Clustering of iEEG Data for Epileptic Patients
- Deep neural networks for seizure detection
- Spiking Neural Network for Autonomous Navigation
- Event-Driven Convolutional Neural Network Modular Accelerator
- Design of an Ultra-Reliable Low-Latency Modem
- Towards global Brain-Computer Interfaces
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core
- Level Crossing ADC For a Many Channels Neural Recording Interface
- Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
- Monocular Vision-based Object Following on Nano-size Robotic Blimp
- A Waypoint-based Navigation System for Nano-Size UAVs in GPS-denied Environments
- Real-Time Implementation of Quantum State Identification using an FPGA
- Autonomous Sensors For Underwater Monitoring In Smart Navy Systems
- Variable Bit Precision Logic for Deep Learning and Artificial Intelligence
- VLSI Implementation Polar Decoder using High Level Synthesis
- Smart Wearable System For Vital Sign Monitoring Exploiting On Board and Cloud Machine Learning
- PVT Dynamic Adaptation in PULPv3
- Passive and Self Sustaining Receivers For On and Intra Body Communication For Wearable Sensors Networks
- A Wearable System To Control Phone And Electronic Device Without Hands
- Ultra Low Power Conversion Circuit For Batteryless Applications
- Using Motion Sensors to Support Indoor Localization
- Birds Long Term Monitoring With Ultra Low Power Wireless Sensor Node
ASIC Design
- An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
- VLSI Implementation of a 5G Ciphering Accelerator
- Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
- RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB
- Spiking Neural Network for Autonomous Navigation
- Event-Driven Convolutional Neural Network Modular Accelerator
- Design of an Ultra-Reliable Low-Latency Modem
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
- Level Crossing ADC For a Many Channels Neural Recording Interface
- Scalable Heterogeneous L1 Memory Interconnect for Smart Accelerator Coupling in Ultra-Low Power Multicores
- Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
- Machine Learning-based Compressive Sensing Vehicle Location Tracking ASIC Design
- High-Throughput Channel Coding & Decoding for V2X Communications
- High-Speed Channel Estimation & Tracking for V2X Communications
- Resilient Brain-Inspired Hyperdimensional Computing Architectures
- Variable Bit Precision Logic for Deep Learning and Artificial Intelligence
- Single-Bit-Synapse Spiking Neural System-on-Chip
FPGA Design
- Efficient Synchronization of Manycore Systems (M/1S)
- Design of an Ultra-Reliable Low-Latency Modem
- LightProbe - 200G Remote DMA for GPU FPGA Data Transfers
- Machine Learning-based Compressive Sensing Vehicle Location Tracking ASIC Design
- Digital Front End Design & Frequency Offset Estimation for V2X Communications
- High-Throughput Channel Coding & Decoding for V2X Communications
- High-Speed Channel Estimation & Tracking for V2X Communications
- Physics is looking for PULP
- OTDOA Positioning for LTE Cat-M
- High Speed FPGA Trigger Logic for Particle Physics Experiments
- Real-Time Implementation of Quantum State Identification using an FPGA
- Resilient Brain-Inspired Hyperdimensional Computing Architectures
- VLSI Implementation Polar Decoder using High Level Synthesis
- Compressed Sensing vs JPEG
System Design
- Short Range Radars For Biomedical Application
- Smart Patch For Heath Care And Rehabilitation
- Autonomus Drones With Novel Sensors And Ultra Wide Band
- Machine Learning on Ultrasound Images
- Outdoor Precision Object Tracking for Rockfall Experiments
- Time Gain Compensation for Ultrasound Imaging
- Minimum Variance Beamforming for Wearable Ultrasound Probes
- Machine Learning for extracting Muscle features using Ultrasound
- Real-Time Motor-Imagery Classification Using Neuromorphic Processor
- Pressure and acoustic Smart Sensors Network for Wind Turbines Monitoring
- Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications
- Design Of A Biomarker Assay Based On Responsive Magnetic Nanoparticles
- High-throughput Embedded System For Neurotechnology in collaboration with INI
- Neuromorphic Intelligence In An Embedded System in Collaboration with AiCTX
- Adversarial Attacks Against Deep Neural Networks In Wearable Cameras
- Wearable Smart Camera With Deep Learning Algorithms For Automatic Detecion
- Visualizing Functional Microbubbles using Ultrasound Imaging
- Energy Efficient Smart Devices For Construction Building Maintenance Hilti Collaboration
- LightProbe - 200G Remote DMA for GPU FPGA Data Transfers
- Improving Cold-Start in Batteryless And Energy Harvesting Systems
- Design and Evaluation of a Small Size Avalanche Beacon
- Edge Computing for Long-Term Wearable Biomedical Systems
- Optogenetics And Game Theory Applied To Small Side Bird Using Smart Sensing
- Wireless Sensing With Long Range Comminication (LoRa)
- Indoor Smart Tracking of Hospital instrumentation
- A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications
- Physics is looking for PULP
- Embedded Gesture Recognition Using Novel Mini Radar Sensors
- Contextual Intelligence on Resource-constraint Bluetooth LE IoT Devices
- An Industrial-grade Bluetooth LE Mesh Network Solution
- Zero Power Touch Sensor and Reciever For Body Communication
- Wake Up Radio For Energy Efficient Communication System and IC Design
- A Wireless Sensor Network for HPC monitoring
- High Speed FPGA Trigger Logic for Particle Physics Experiments
- Low Power One bit Microphone for Acoustic Imaging Using A Parallel Processor
- Low Power Geolocalization And Indoor Localization
- Real-Time Implementation of Quantum State Identification using an FPGA
- Neural Networks Framwork for Embedded Plattforms
- Autonomous Sensors For Underwater Monitoring In Smart Navy Systems
- Autonomous Sensing For Trains In The IoT Era
- Smart Wearable System For Vital Sign Monitoring Exploiting On Board and Cloud Machine Learning
- Desing and Implementation Of Long Lasting Key Finder With Bleetooth Low Energy
- Radio Signal Direction Detection For Smart Glasses For Augmented Reality Applications
- PVT Dynamic Adaptation in PULPv3
- Passive and Self Sustaining Receivers For On and Intra Body Communication For Wearable Sensors Networks
- A Wearable System To Control Phone And Electronic Device Without Hands
- Towards The Integration of E-skin into Prosthetic Devices
- Ultra Low Power Conversion Circuit For Batteryless Applications
- Towards Self Sustainable UAVs
- Using Motion Sensors to Support Indoor Localization
- Low Power Neural Network For Multi Sensors Wearable Devices
- Bateryless Heart Rate Monitoring
- Birds Long Term Monitoring With Ultra Low Power Wireless Sensor Node
- Ultra-Efficient Visual Classification on Movidius Myriad2
- A Wearable System for long term monitoring of human physiological parameters with E skin sensors
- Autonomous Smart Watches: Toward an ultra low power microphone detector with events classification
- Autonomous Smart Watches: Hardware and Software Desing
- A Wireless Sensor Network for a Smart LED Lighting control
- Ultra-High-Efficiency Power Supply Management for Ultra-Low-Power Systems on Chip
- Real-Time Pedestrian Detection For Privacy Enhancement
- Thermal Control of Mobile Devices
- Android reliability governor
- Infrared Wake Up Radio
- Ambient RF Energy harvesting for Wireless Sensor Network
- Ultra Low Power Wake Up Radio for Wireless Sensor Network
Software Development
- Improved State Estimation on PULP-based Nano-UAVs
- Enabling Standalone Operation for a Mobile Health Platform
- Design and Implementation of a multi-mode multi-master I2C peripheral
- Optimal System Duty Cycling for a Mobile Health Platform
- Monocular Vision-based Object Following on Nano-size Robotic Blimp
- A Waypoint-based Navigation System for Nano-Size UAVs in GPS-denied Environments
- A Wireless Sensor Network for HPC monitoring
- Covariant Feature Detector on Parallel Ultra Low Power Architecture
Processor Design
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
- Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
- Enabling Standalone Operation for a Mobile Health Platform
- Design and Implementation of a multi-mode multi-master I2C peripheral
- Optimal System Duty Cycling for a Mobile Health Platform
Cryptography
Telecommunication Circuits
- VLSI Implementation of a 5G Ciphering Accelerator
- Design of an Ultra-Reliable Low-Latency Modem
- OTDOA Positioning for LTE Cat-M
- VLSI Implementation Polar Decoder using High Level Synthesis
Others
- RVfplib
- Exploring feature selection and classification algorithms for ultra-low-power closed-loop systems for epilepsy control
- Evaluating memory access pattern specializations in OoO, server-grade cores (M)
- Evaluating An Ultra low Power Vision Node
- Hypervisor Extension for Ariane (M)
- Mapping Networks on Reconfigurable Binary Engine Accelerator
- Probabilistic training algorithms for quantized neural networks
- Exploring schedules for incremental and annealing quantization algorithms
- RISC-V base ISA for ultra-low-area cores (2-3G)
- IP-Based SoC Generation and Configuration (1-3S/B)
- Efficient Search Design for Hyperdimensional Computing
- Efficient TNN compression
- SystemVerilog formatter for our LowRISC-based guidelines (2-3G)
- Coherence-Capable Write-Back L1 Data Cache for Ariane (M)
- PREM Runtime Scheduling Policies
- Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
- Event-Driven Vision on an embedded platform
- Smart Meters
- Knowledge Distillation for Embedded Machine Learning
- Hardware Constrained Neural Architechture Search
- IBM Research
- Combining Spiking Neural Networks with Hyperdimensional Computing for Autonomous Navigation
- Improved State Estimation on PULP-based Nano-UAVs
- Classification of Evoked Local-Field Potentials in Rat Barrel Cortex using Hyper-dimensional Computing
- Data Augmentation Techniques in Biosignal Classification
- Compression of iEEG Data
- BCI-controlled Drone
- Contrastive Learning for Self-supervised Clustering of iEEG Data for Epileptic Patients
- Nanoelectrode array biosensors - programmable non-overlapping clocks generator project
- Accurate deep learning inference using computational memory
- Deep neural networks for seizure detection
- Towards global Brain-Computer Interfaces
- Extending the RISCV backend of LLVM to support PULP Extensions
- Compiler Profiling and Optimizing
- PREM Intervals and Loop Tiling
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core
- SmartRing
- PREM on PULP
- AMZ Driverless Competition Embedded Systems Projects
- BLISS - Battery-Less Identification System for Security
- Monocular Vision-based Object Following on Nano-size Robotic Blimp
- A Waypoint-based Navigation System for Nano-Size UAVs in GPS-denied Environments
- Hyper Meccano: Acceleration of Hyperdimensional Computing
- Tiny CNNs for Ultra-Efficient Object Detection on PULP
- OpenRISC SoC for Sensor Applications
- Covariant Feature Detector on Parallel Ultra Low Power Architecture
- Kinetic Energy Harvesting For Autonomous Smart Watches
- Hardware Support for IDE in Multicore Environment
- Audio DAC Conversion Jitter Measurement System
- Hybrid Analog/Digital Leveling Loop for Very-Low-Distortion Oscillator
- Wiederverwendung (reuse) ganzer Funktionsblöcke beim VLSI-Entwurf
- Praxisgerechte Berechnung von Switching Noise in VLSI-Schaltungen
- Variability Tolerant Ultra Low Power Cluster
Active Projects
These are the projects that are currently active
- Next Generation Synchronization Signals
- Low Latency Brain-Machine Interfaces
- ISA extensions in the Snitch Processor for Signal Processing (M)
- PULP in space - Fault Tolerant PULP System for Critical Space Applications
- A Snitch-based Compute Accelerator for HERO (M/1-2S)
- A Flexible Peripheral System for High-Performance Systems on Chip (M)
- Channel Estimation for 5G Cellular IoT and Fast Fading Channels
- Hyper-Dimensional Computing Based Predictive Maintenance
- Memory Augmented Neural Networks in Brain-Computer Interfaces
- Advanced 5G Repetition Combining
- An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications
Completed Projects
These are projects that were completed in the last few years
2015
- Hardware Accelerated Derivative Pricing
- Glitches Reduce Listening Time of Your iPod
- FFT-based Convolutional Network Accelerator
- Real-Time Optical Flow Using Neural Networks
- EvaLTE: A 2G/3G/4G Cellular Transceiver FMC
- Synchronisation and Cyclic Prefix Handling For LTE Testbed
- An FPGA-Based Testbed for 3G Mobile Communications Receivers
- Reading The GSM Beacon Carrier with OsmocomBB and stoneEDGE
- Baseband Meets CPU
- Active-Set QP Solver on FPGA
- Vector Processor for In-Memory Computing
- StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC
- Hardware/software co-programming on the Parallella platform
- Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA
- Time and Frequency Synchronization in LTE Cat-0 Devices
- Real-Time Stereo to Multiview Conversion
2014
- EvalEDGE: A 2G Cellular Transceiver FMC
- Real-Time Stereo to Multiview Conversion
- Design and Implementation of a Convolutional Neural Network Accelerator ASIC
- Design and Implementation of an Approximate Floating Point Unit
2013
- RazorEDGE: An Evolved EDGE DBB ASIC
- Real-Time Stereo to Multiview Conversion
- NORX - an AEAD algorithm for the CAESAR competition
- A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography
- SHAre - An application Specific Instruction Set Processor for SHA-2/3
- Quantum Key Secured 100 Gbit/s Payload Encryption and its High-Speed Network Interfaces
- Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment
- Real-time View Synthesis using Image Domain Warping
- Ultra-low power processor design
2012
- A Multiview Synthesis Core in 65 nm CMOS
- Real-time View Synthesis using Image Domain Warping
- High-Throughput Authenticated Encryption Architectures based on Block Ciphers
