Difference between revisions of "Digital"

Revision as of 16:48, 10 November 2020

Topic List

• High Performance SoCs
  • Heterogeneous Acceleration Systems
• Energy Efficient SoCs
• Hardware Acceleration
  • Acceleration and Transprecision
• Biomedical Circuits, Systems, and Applications
  • Human Intranet
  • Digital Medical Ultrasound Imaging
• SW/HW Predictability and Security
  • Predictable Execution
  • Cryptographic Hardware
• Deep Learning Acceleration
  • Event-Driven Computing
• Embedded Systems and autonomous UAVs
  • Energy Efficient Autonomous UAVs
  • Low Power Embedded Systems
  • Embedded Artificial Intelligence:Systems And Applications

External Collaborations

Topic List

• Biomedical System on Chips
• Wireless Communication Systems for the IoT
• IBM_Research
  • In-Memory Computing
• Students' International Competitions: F1(AMZ), Swissloop, Educational Rockets
• Physics is looking for PULP

Topics for Projects

• High Performance SoCs
• Computer Architecture
• Acceleration and Transprecision
• Heterogeneous Acceleration Systems
• Event-Driven Computing
• Predictable Execution
• Low Power Embedded Systems
• Embedded Artificial Intelligence:Systems And Applications
• Wireless Communication Systems for the IoT
• Energy Efficient Autonomous UAVs
• Biomedical System on Chips
• Digital Medical Ultrasound Imaging
• Cryptographic Hardware
• Deep Learning Acceleration
• Human Intranet
• IBM Research

Active Projects

These are the projects that are currently active:

• Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
• Manycore System on FPGA (M/S/G)
• Physical Implementation of Ara, PULP's Vector Machine (1-2S)
• Transforming MemPool into a CGRA (M)
• Efficient TNN compression
• Event-Driven Vision on an embedded platform
• LLVM and DaCe for Snitch (1-2S)
• Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G)
• A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
• An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
• Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
• Multi issue OoO Ariane Backend (M)
• Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
• ASIC Development of 5G-NR LDPC Decoder
• Next Generation Synchronization Signals
• Low Latency Brain-Machine Interfaces
• PULP in space - Fault Tolerant PULP System for Critical Space Applications
• Channel Estimation for 5G Cellular IoT and Fast Fading Channels
• Hyper-Dimensional Computing Based Predictive Maintenance
• Memory Augmented Neural Networks in Brain-Computer Interfaces
• Advanced 5G Repetition Combining
• An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications

Completed Projects

These are projects that were completed in the last few years:

2019

• Hardware Accelerators for Lossless Quantized Deep Neural Networks
• Floating-Point Divide & Square Root Unit for Transprecision
• TCNs vs. LSTMs for Embedded Platforms
• An Energy Efficient Brain-Computer Interface using Mr.Wolf
• Toward hyperdimensional active perception: learning compressed sensorimotor control by demonstration
• Exploring Algorithms for Early Seizure Detection
• Ternary Weights Engine For Efficient Many Channels Spike Sorting Applications
• Indoor Positioning with Bluetooth
• Improving Resiliency of Hyperdimensional Computing
• Toward Superposition of Brain-Computer Interface Models

2018

• Digital Audio Interface for Smart Intensive Computing Triggering
• Shared Correlation Accelerator for an RF SoC
• IoT Turbo Decoder
• BigPULP: Shared Virtual Memory Multicluster Extensions
• Creating a HDMI Video Interface for PULP
• Interference Cancellation for EC-GSM-IoT

2017

• A computational memory unit using phase-change memory devices
• Deep Learning for Brain-Computer Interface
• Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration
• Turbo Equalization for Cellular IoT
• Sensor Fusion for Rockfall Sensor Node
• Development of a Rockfall Sensor Node
• FPGA Optimizations of Dense Binary Hyperdimensional Computing
• Fast and Accurate Multiclass Inference for Brain–Computer Interfaces
• A Wireless Sensor Network for a Smart Building Monitor and Control
• BigPULP: Multicluster Synchronization Extensions
• Sub Noise Floor Channel Estimation for the Cellular Internet of Things
• PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker
• StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC

2016

• A Recurrent Neural Network Speech Recognition Chip
• Efficient NB-IoT Uplink Design
• Internet of Things Network Synchronizer
• Accelerator for Boosted Binary Features
• Accelerator for Spatio-Temporal Video Filtering
• Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea
• Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors
• System Analysis and VLSI Design of NB-IoT Baseband Processing
• High-speed Scene Labeling on FPGA
• Learning Image Decompression with Convolutional Networks
• FPGA System Design for Computer Vision with Convolutional Neural Networks
• PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB
• Implementing Hibernation on the ARM Cortex M0
• High-Throughput Hardware Implementations of Authenticated Encryption Algorithms
• Spatio-Temporal Video Filtering
• PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions

2015

• Hardware Accelerated Derivative Pricing
• Glitches Reduce Listening Time of Your iPod
• FFT-based Convolutional Network Accelerator
• Real-Time Optical Flow Using Neural Networks
• EvaLTE: A 2G/3G/4G Cellular Transceiver FMC
• Synchronisation and Cyclic Prefix Handling For LTE Testbed
• An FPGA-Based Testbed for 3G Mobile Communications Receivers
• Reading The GSM Beacon Carrier with OsmocomBB and stoneEDGE
• Baseband Meets CPU
• Active-Set QP Solver on FPGA
• Vector Processor for In-Memory Computing
• StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC
• Hardware/software co-programming on the Parallella platform
• Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA
• Time and Frequency Synchronization in LTE Cat-0 Devices
• Real-Time Stereo to Multiview Conversion

2014

• EvalEDGE: A 2G Cellular Transceiver FMC
• Real-Time Stereo to Multiview Conversion
• Design and Implementation of a Convolutional Neural Network Accelerator ASIC
• Design and Implementation of an Approximate Floating Point Unit

2013

• RazorEDGE: An Evolved EDGE DBB ASIC
• Real-Time Stereo to Multiview Conversion
• NORX - an AEAD algorithm for the CAESAR competition
• A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography
• SHAre - An application Specific Instruction Set Processor for SHA-2/3
• Quantum Key Secured 100 Gbit/s Payload Encryption and its High-Speed Network Interfaces
• Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment
• Real-time View Synthesis using Image Domain Warping
• Ultra-low power processor design

2012

• A Multiview Synthesis Core in 65 nm CMOS
• Real-time View Synthesis using Image Domain Warping
• High-Throughput Authenticated Encryption Architectures based on Block Ciphers

2011

• Compressed Sensing Reconstruction on FPGA
• A Multiview Synthesis Core in 65 nm CMOS
• Real-time View Synthesis using Image Domain Warping
• Putting Together What Fits Together - GrÆStl