Digital Front End Design & Frequency Offset Estimation for V2X Communications
Due to high-speed mobility, sampling instance and frequency offset estimation play a crucial role in the overall performance of the digital baseband receiver in V2X communications.
An FPGA-based testbed already exists at the IIS, though without any realistic interfaces to frontend and higher layers. The objective of this project is to extend the existing FPGA testbed to include the digital front end along with a fast and accurate frequency synchronization scheme. The analog frontend will be provided.
- VLSI I
- Interest in digital design
- Background in signal processing or digital communications
- VLSI II (optional)
- 20% Theory & Simulation
- 60% ASIC/FPGA Design
- 20% EDA tools