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Evolved EDGE Physical Layer Incremental Redundancy Architecture

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Top: Simulation results for coding schemes MCS-9 and DAS-12 in order to evalute IR performance. Bottom: High-level dedicated IR architecture storing punctured RLC blocks.

Date

2012

Personnel

Benjamin Weber
Christian Benkeser
Harald Kröll
Christoph Roth

Funding

KTI 11376.1

Partners

ACP

Summary

The latest 2.75G enhancements in the GSM standard, also referred to as Evolved EDGE comprise higher order modulation schemes and turbo coding. The type II hybrid ARQ or Incremental Redundancy (IR) mechanism aids Evolved EDGE systems to achieve higher average throughput. A Base Transceiver Station (BTS) transmits punctured Radio Link Control (RLC) blocks packed on bursts to a Mobile Station (MS). In the MS, a RLC block, typically represented as soft information, is stored in case decoding proves unsuccessful. Subsequently, the BTS retransmits the RLC block with a different puncturing pattern and the MS combines the soft information of the current transmission and the previously stored version. In case decoding fails again, the procedure is repeated.

In a classical GSM/EDGE implementation IR operations are distributed over Physical Layer (PHY), Layer 2 (L2)/ Layer 3 (L3), and erroneous RLC blocks are stored in an external memory. An IR control unit is running on a L2/L3 system processor and the unit where RLC blocks are processed for IR is attached to the system processor. The decoding of the RLC blocks takes place on a PHY Digital Signal Processor (DSP) and an accelerator attached to it.

In this work, simulations were run in order to evaluate IR performance and a dedicated hardware architecture incorporating all IR related operations in the PHY alone was implemented. This architecture hides all IR complexity from L2/L3 without the use of external components. Naturally, this simplicity eases L2/L3 protocol design.

Publications

  • Benjamin Weber, Harald Kröll, Christian Benkeser, and Qiuting Huang. On the Mapping of Incremental Redundancy into a Physical Layer ASIC. Journal of Signal Processing Systems, 78(3):299–312, October 2014. DOI: 10.1007/s11265-014-0949-1
  • Benjamin Weber, Harald Kröll, Christian Benkeser, and Qiuting Huang. An Efficient Incremental Redundancy Implementation for 2.75G Evolved EDGE. In 2013 Wireless Innovation Forum European Conference on Communications Technologies and Software Defined Radio (SDR-WInnComm-Europe 2013), pages 21–26, Munich, Germany, June 2013.