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Revision as of 16:31, 17 July 2016 by Weberbe (talk | contribs) (Aspired testbed setup with L2/L3 processing on PULP as well as dedicated DBB processing on an FPGA and RF on evaLTE FMC module.)
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Aspired testbed setup with L2/L3 processing on PULP as well as dedicated DBB processing on an FPGA and RF on evaLTE FMC module.

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current16:31, 17 July 2016Thumbnail for version as of 16:31, 17 July 20161,292 × 1,113 (75 KB)Weberbe (talk | contribs)Aspired testbed setup with L2/L3 processing on PULP as well as dedicated DBB processing on an FPGA and RF on evaLTE FMC module.
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