GRAND Hardware Implementation
From iis-projects
Short Description
Guessing random additive noise decoding (GRAND) is an emerging maximum likelihood (ML) decoding technique. The idea of GRAND is to efficiently guess the noise that corrupted a transmitted codeword. The goal of this project is to develop a better GRAND algorithm that improves the guessing accuracy. The performance evaluation of the algorithm must be carried out in our Matlab framework based on the Bit-Error-Rate (BER) figure. As a second part of the project, the algorithm must be transformed in an efficient hardware architecture. The HDL implementation can be done with System Verilog. Then a synthesis must be carried out as well as the backend routine for the ASIC fabrication.
Status: Available
- Looking for 1-2 Semester/Master students
- Contact: Darja Nonaca, dnonaca@iis.ee.ethz.ch
Prerequisites
- Communication Systems (or a similar course)
- Algebra and Error-Correcting Codes (recommended)
- VLSI 1
- VLSI 3 (recommended)
