Difference between revisions of "Heterogeneous SoCs"
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Revision as of 16:13, 14 November 2017
Available Projects
- Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S)
- Cycle-Accurate Event-Based Simulation of Snitch Core
- Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M)
- Fast Simulation of Manycore Systems (1S)
Projects In Progress
Completed Projects
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1-3S/B)
- Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M)
- Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M)
- Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems
- Efficient Synchronization of Manycore Systems (M/1S)
- Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
- Transforming MemPool into a CGRA (M)
- Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G)
- LLVM and DaCe for Snitch (1-2S)
- Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
- A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
- ISA extensions in the Snitch Processor for Signal Processing (M)
- A Snitch-based Compute Accelerator for HERO (M/1-2S)
- MemPool on HERO (1S)
- Implementation of a Heterogeneous System for Image Processing on an FPGA (S)
- HERO: TLB Invalidation
- BigPULP: Shared Virtual Memory Multicluster Extensions
- BigPULP: Multicluster Synchronization Extensions
- Smart Virtual Memory Sharing
- PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker
- PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB
- PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions
