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High-Throughput Hardware Implementations of Authenticated Encryption Algorithms

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Asic caesar.jpg

Short Description

These days, security breaches are omnipresent in our daily news thanks to the NSA and others. Therefore, new cryptographic algorithms need to be developed and judged with regard to their cryptographic strengths as well as concerning their software and hardware performance. The CAESAR competition aims at finding a portfolio of new algorithms providing confidentiality and authenticity of data transmitted over insecure channels such as the Internet.

Your task in this project will be to develop hardware architectures of these, already existing algorithms, in order to achieve throughputs of 100Gbit/s and even more, either as an ASIC or as part of an FPGA project. You will compare your personal results with previous work from others and try to beat today's de-facto standards such as AES. If you are interested in working on hardware implementations of state-of-the-art security algorithms, which may become part of any future credit card or WiFi standard, feel free to contact the responsible person listed below.

Status: Available

Prerequisites

  • VLSI I
  • Attend VLSI II (for ASIC designs)
  • Basic C/C++ Programming Skills

Character

  • 10% Theory
  • 20% C/C++
  • 40% HDL Design
  • 30% ASIC/FPGA Implementation

Professor