Personal tools

Difference between revisions of "High Performance SoCs"

From iis-projects

Jump to: navigation, search
 
(14 intermediate revisions by 3 users not shown)
Line 1: Line 1:
==Contact Information==
+
==High-Performance Systems-on-Chip==
 +
 
 +
[[File:Snitch-bd.png|thumb|350px|The ''Snitch'' cluster couples tiny RISC-V ''Snitch'' cores with performant double-precision FPUs to minimize the control-to-compute ratio; it uses hardware loop buffers and stream semantic registers to achieve almost full FPU utilization.]]
 +
[[File:Floorplan_baikonur.png|thumb|350px|''Baikonur'', a 22 nm chip integrating two application-grade RISC-V Ariane cores and 3 Snitch clusters with 8 cores each.]]
 +
[[File:Manticore_concept.png|thumb|350px|Concept art for ''Manticore'', a Snitch-based 22 nm system with 4096 cores on multiple chiplets and with HBM2 memory.]]
 +
 
 +
Today, a multitude of data-driven applications such as machine learning, scientific computing, and big data demand an ever-increasing amount of '''parallel floating-point performance''' from computing systems. Increasingly, such applications must scale across a wide range of applications and energy budgets, from supercomputers simulating next week's weather to your smartphone cameras correcting for low light conditions.
 +
 
 +
This brings challenges on multiple fronts:
 +
 
 +
* '''Energy Efficiency''' becomes a major concern: As logic density increases, supplying these systems with energy and managing their heat dissipation requires increasingly complex solutions.
 +
 
 +
* '''Memory bandwidth and latency''' become a major bottleneck as the amount of processed data increases. Despite continuous advances, memory lags behind computing in scaling, and many data-driven problems today are memory-bound.
 +
 
 +
* '''Parallelization and scaling''' bring challenges of their own: on-chip interconnects may introduce significant area and performance overheads as they grow, and both the data and instruction streams of cores may compete for valuable memory bandwidth and interfere in a destructive way.
 +
 
 +
While all state-of-the-art high-performance computing systems are constrained by the above issues, they are also subject to a fundamental trade-off between efficiency and flexibility. This forms a design space which includes the following paradigms:
 +
 
 +
* '''Accelerators''' are designed to do one thing very well: they are very energy efficient and performant and usually offer predetermined data movement. However, they are not or barely programmable, inflexible, and monolithic in their design.
 +
 
 +
* '''Superscalar Out-of-Order CPUs''', on the other end, provide extreme flexibility, full programmability, and reasonable performance across various workloads. However, they require large area and energy overheads for a given performance, use memory inefficiently, and are often hard to scale well to manycore systems.
 +
 
 +
* '''GPUs''' are parallel and data-oriented by design, yet still meaningfully programmable, aiming for a sweet-spot between scalability, efficiency, and programmability. However, are still subject to memory access challenges and often require manual memory management for decent performance.
 +
 
 +
'''How can we further improve on these existing paradigms?''' Can we design decently efficient and performant, yet freely programmable systems with scalable, performant memory systems?
 +
 
 +
If these questions sound intriguing to you, consider joining us for a project or thesis! You can find currently available projects and our contact information below.
 +
 
 +
==Our Activities==
 +
 
 +
We are primarily interested in '''architecture design and hardware implementation''' for high-performance systems. However, ensuring high performance requires us to consider the '''entire hardware-software stack''':
 +
 
 +
* '''HPC Software''': Design and porting of high-performance applications, benchmarks, compiler tools, and operating systems (Linux) to our hardware.
 +
* '''Hardware-software codesign''': Design of performance-aware algorithms and kernels and hardware that can be efficiently programmed for use in processor-based systems.
 +
* '''Architecture''': RTL implementation of energy-efficient designs with an emphasis on high utilization and throughput, as well as on efficient interoperability with existing IPs.
 +
* '''SoC design and Implementation''': Design of full high-performance systems-on-chips; implementation and tapeout on modern silicon technologies such as TSMC's 65 nm and GlobalFoundries' 22 nm nodes.
 +
* '''IC testing and Board-Level design''': Testing of the returning chips with industry-grade automated test equipment (ATE) and design of system-level demonstrator boards.
 +
 
 +
Our current interests include systems with '''low control-to-compute ratios''', high-performance '''on-chip interconnects''', and '''scalable many-core systems'''. However, we are always happy to explore new domains; if you have an interesting idea, contact us and we can discuss it in detail!
 +
 
 +
==Who are we==
  
 
{|
 
{|
Line 10: Line 50:
 
|}
 
|}
  
 +
{|
 +
| style="padding: 10px" | [[File:Tbenz_face_pulp_team.jpg|frameless|left|96px]]
 +
|
 
===[[:User:Tbenz | Thomas Benz]]===
 
===[[:User:Tbenz | Thomas Benz]]===
 
* '''e-mail''': [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]
 
* '''e-mail''': [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]
 
* '''phone''': +41 44 632 05 18
 
* '''phone''': +41 44 632 05 18
 
* '''office''': ETZ J85
 
* '''office''': ETZ J85
 +
|}
  
 +
{|
 +
| style="padding: 10px" | [[File:Nwistoff_face_pulp_team.JPG|frameless|left|96px]]
 +
|
 
===[[:User:Nwistoff | Nils Wistoff]]===
 
===[[:User:Nwistoff | Nils Wistoff]]===
 
* '''e-mail''': [mailto:nwistoff@iis.ee.ethz.ch nwistoff@iis.ee.ethz.ch]
 
* '''e-mail''': [mailto:nwistoff@iis.ee.ethz.ch nwistoff@iis.ee.ethz.ch]
 
* '''phone''': +41 44 632 06 75
 
* '''phone''': +41 44 632 06 75
 
* '''office''': ETZ J85
 
* '''office''': ETZ J85
 +
|}
 +
 +
{|
 +
| style="padding: 10px" | [[File:Mperotti_face_pulp_team.jpg|frameless|left|96px]]
 +
|
 +
===[[:User:Mperotti | Matteo Perotti]]===
 +
* '''e-mail''': [mailto:mperotti@iis.ee.ethz.ch mperotti@iis.ee.ethz.ch]
 +
* '''phone''': +41 44 632 05 25
 +
* '''office''': ETZ J85
 +
|}
 +
 +
{|
 +
| style="padding: 10px" | [[File:Sriedel_face_pulp_team.jpg|frameless|left|96px]]
 +
|
 +
===[[:User:Sriedel | Samuel Riedel]]===
 +
* '''e-mail''': [mailto:sriedel@iis.ee.ethz.ch sriedel@iis.ee.ethz.ch]
 +
* '''phone''': +41 44 632 65 69
 +
* '''office''': ETZ J71.2
 +
|}
 +
 +
{|
 +
| style="padding: 10px" | [[File:Matheusd_face_1to1.png|frameless|left|96px]]
 +
|
 +
===[[:User:Matheusd | Matheus Cavalcante]]===
 +
* '''e-mail''': [mailto:matheusd@iis.ee.ethz.ch matheusd@iis.ee.ethz.ch]
 +
* '''phone''': +41 44 632 54 96
 +
* '''office''': ETZ J69.2
 +
|}
  
 +
{|
 +
| style="padding: 10px" | [[File:Akurth_face_pulp_team.jpeg|frameless|left|96px]]
 +
|
 +
===[[:User:Akurth | Andreas Kurth]]===
 +
* '''e-mail''': [mailto:akurth@iis.ee.ethz.ch akurth@iis.ee.ethz.ch]
 +
* '''phone''': +41 44 632 04 87
 +
* '''office''': ETZ J69.2
 +
|}
 +
 +
{|
 +
| style="padding: 10px" | [[File:Zarubaf_face_pulp_team.jpg|frameless|left|96px]]
 +
|
 +
===[[:User:Zarubaf | Florian Zaruba]]===
 +
* '''e-mail''': [mailto:zarubaf@iis.ee.ethz.ch zarubaf@iis.ee.ethz.ch]
 +
* '''phone''': +41 44 632 65 56
 +
* '''office''': ETZ J89
 +
|}
 +
 +
{|
 +
| style="padding: 10px" | [[File:Fschuiki_face_pulp_team.jpg|frameless|left|96px]]
 +
|
 +
===[[:User:Fschuiki | Fabian Schuiki]]===
 +
* '''e-mail''': [mailto:fschuiki@iis.ee.ethz.ch fschuiki@iis.ee.ethz.ch]
 +
* '''phone''': +41 44 632 67 89
 +
* '''office''': ETZ J89
 +
|}
  
 
<!--
 
<!--
Line 35: Line 136:
 
category = High Performance SoCs
 
category = High Performance SoCs
 
suppresserrors=true
 
suppresserrors=true
 +
ordermethod=sortkey
 +
order=ascending
 
</DynamicPageList>
 
</DynamicPageList>
  
Line 42: Line 145:
 
category = Digital
 
category = Digital
 
category = High Performance SoCs
 
category = High Performance SoCs
suppresserrors=true
+
suppresserrors=false
 +
ordermethod=sortkey
 +
order=ascending
 
</DynamicPageList>
 
</DynamicPageList>
  
Line 51: Line 156:
 
category = High Performance SoCs
 
category = High Performance SoCs
 
suppresserrors=true
 
suppresserrors=true
 +
</DynamicPageList>
 +
 +
===Reserved Projects===
 +
<DynamicPageList>
 +
category = Reserved
 +
category = Digital
 +
category = High Performance SoCs
 +
suppresserrors=true
 +
ordermethod=sortkey
 +
order=ascending
 
</DynamicPageList>
 
</DynamicPageList>

Latest revision as of 16:21, 11 November 2020

High-Performance Systems-on-Chip

The Snitch cluster couples tiny RISC-V Snitch cores with performant double-precision FPUs to minimize the control-to-compute ratio; it uses hardware loop buffers and stream semantic registers to achieve almost full FPU utilization.
Baikonur, a 22 nm chip integrating two application-grade RISC-V Ariane cores and 3 Snitch clusters with 8 cores each.
Concept art for Manticore, a Snitch-based 22 nm system with 4096 cores on multiple chiplets and with HBM2 memory.

Today, a multitude of data-driven applications such as machine learning, scientific computing, and big data demand an ever-increasing amount of parallel floating-point performance from computing systems. Increasingly, such applications must scale across a wide range of applications and energy budgets, from supercomputers simulating next week's weather to your smartphone cameras correcting for low light conditions.

This brings challenges on multiple fronts:

  • Energy Efficiency becomes a major concern: As logic density increases, supplying these systems with energy and managing their heat dissipation requires increasingly complex solutions.
  • Memory bandwidth and latency become a major bottleneck as the amount of processed data increases. Despite continuous advances, memory lags behind computing in scaling, and many data-driven problems today are memory-bound.
  • Parallelization and scaling bring challenges of their own: on-chip interconnects may introduce significant area and performance overheads as they grow, and both the data and instruction streams of cores may compete for valuable memory bandwidth and interfere in a destructive way.

While all state-of-the-art high-performance computing systems are constrained by the above issues, they are also subject to a fundamental trade-off between efficiency and flexibility. This forms a design space which includes the following paradigms:

  • Accelerators are designed to do one thing very well: they are very energy efficient and performant and usually offer predetermined data movement. However, they are not or barely programmable, inflexible, and monolithic in their design.
  • Superscalar Out-of-Order CPUs, on the other end, provide extreme flexibility, full programmability, and reasonable performance across various workloads. However, they require large area and energy overheads for a given performance, use memory inefficiently, and are often hard to scale well to manycore systems.
  • GPUs are parallel and data-oriented by design, yet still meaningfully programmable, aiming for a sweet-spot between scalability, efficiency, and programmability. However, are still subject to memory access challenges and often require manual memory management for decent performance.

How can we further improve on these existing paradigms? Can we design decently efficient and performant, yet freely programmable systems with scalable, performant memory systems?

If these questions sound intriguing to you, consider joining us for a project or thesis! You can find currently available projects and our contact information below.

Our Activities

We are primarily interested in architecture design and hardware implementation for high-performance systems. However, ensuring high performance requires us to consider the entire hardware-software stack:

  • HPC Software: Design and porting of high-performance applications, benchmarks, compiler tools, and operating systems (Linux) to our hardware.
  • Hardware-software codesign: Design of performance-aware algorithms and kernels and hardware that can be efficiently programmed for use in processor-based systems.
  • Architecture: RTL implementation of energy-efficient designs with an emphasis on high utilization and throughput, as well as on efficient interoperability with existing IPs.
  • SoC design and Implementation: Design of full high-performance systems-on-chips; implementation and tapeout on modern silicon technologies such as TSMC's 65 nm and GlobalFoundries' 22 nm nodes.
  • IC testing and Board-Level design: Testing of the returning chips with industry-grade automated test equipment (ATE) and design of system-level demonstrator boards.

Our current interests include systems with low control-to-compute ratios, high-performance on-chip interconnects, and scalable many-core systems. However, we are always happy to explore new domains; if you have an interesting idea, contact us and we can discuss it in detail!

Who are we

Paulsc face 1to1.png

Paul Scheffler

Tbenz face pulp team.jpg

Thomas Benz

Nwistoff face pulp team.JPG

Nils Wistoff

Mperotti face pulp team.jpg

Matteo Perotti

Sriedel face pulp team.jpg

Samuel Riedel

Matheusd face 1to1.png

Matheus Cavalcante

Akurth face pulp team.jpeg

Andreas Kurth

Zarubaf face pulp team.jpg

Florian Zaruba

Fschuiki face pulp team.jpg

Fabian Schuiki


Projects

Available Projects


Projects In Progress


Completed Projects


Reserved Projects