Difference between revisions of "High Performance SoCs"
From iis-projects
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* '''office''': ETZ J85 | * '''office''': ETZ J85 | ||
| + | ===[[:User:Zarubaf | Florian Zaruba]]=== | ||
| + | * '''e-mail''': [mailto:zarubaf@iis.ee.ethz.ch zarubaf@iis.ee.ethz.ch] | ||
| + | * '''phone''': +41 44 632 65 56 | ||
| + | * '''office''': ETZ J89 | ||
| + | |||
| + | ===[[:User:Fschuiki | Fabian Schuiki]]=== | ||
| + | * '''e-mail''': [mailto:fschuiki@iis.ee.ethz.ch fschuiki@iis.ee.ethz.ch] | ||
| + | * '''phone''': +41 44 632 67 89 | ||
| + | * '''office''': ETZ J89 | ||
| + | |||
| + | <!-- ===[[:User:Balasr | Robert Balas]]=== --> <!-- TODO @balasr --> | ||
| + | ===Robert Balas=== | ||
| + | * '''e-mail''': [mailto:balasr@iis.ee.ethz.ch balasr@iis.ee.ethz.ch] | ||
| + | * '''phone''': +41 44 632 42 56 | ||
| + | * '''office''': ETZ J78 | ||
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Revision as of 14:50, 22 October 2020
Contents
People
 |
Paul Scheffler
|
Thomas Benz
- e-mail: tbenz@iis.ee.ethz.ch
- phone: +41 44 632 05 18
- office: ETZ J85
Nils Wistoff
- e-mail: nwistoff@iis.ee.ethz.ch
- phone: +41 44 632 06 75
- office: ETZ J85
Florian Zaruba
- e-mail: zarubaf@iis.ee.ethz.ch
- phone: +41 44 632 65 56
- office: ETZ J89
Fabian Schuiki
- e-mail: fschuiki@iis.ee.ethz.ch
- phone: +41 44 632 67 89
- office: ETZ J89
Robert Balas
- e-mail: balasr@iis.ee.ethz.ch
- phone: +41 44 632 42 56
- office: ETZ J78
Projects
Available Projects
- An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
- Evaluating memory access pattern specializations in OoO, server-grade cores (M)
- Hypervisor Extension for Ariane (M)
- RISC-V base ISA for ultra-low-area cores (2-3G)
- IP-Based SoC Generation and Configuration (1-3S/B)
- SystemVerilog formatter for our LowRISC-based guidelines (2-3G)
- Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
- Coherence-Capable Write-Back L1 Data Cache for Ariane (M)
- Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
Projects In Progress
- ISA extensions in the Snitch Processor for Signal Processing (M)
- MemPool on HERO (1S)
- A Snitch-based Compute Accelerator for HERO (M/1-2S)
- A Flexible Peripheral System for High-Performance Systems on Chip (M)
