Difference between revisions of "High Performance SoCs"
From iis-projects
(Created page with "==Contact Information== ===Paul Scheffler=== * '''e-mail''': [mailto:paulsc@iis.ee.ethz.ch paulsc@iis.ee.ethz.ch] * ETZ K61 ===Thomas Benz=== * '''e-mail''': [mailto:tbenz@ii...") |
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* '''e-mail''': [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch] | * '''e-mail''': [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch] | ||
+ | * ETZ K61 | ||
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+ | ===Nils Wistoff=== | ||
+ | * '''e-mail''': [mailto:nwistoff@iis.ee.ethz.ch nwistoff@iis.ee.ethz.ch] | ||
* ETZ K61 | * ETZ K61 | ||
Revision as of 16:32, 27 July 2020
Contents
Contact Information
Paul Scheffler
- e-mail: paulsc@iis.ee.ethz.ch
- ETZ K61
Thomas Benz
- e-mail: tbenz@iis.ee.ethz.ch
- ETZ K61
Nils Wistoff
- e-mail: nwistoff@iis.ee.ethz.ch
- ETZ K61
Projects
Available Projects
- Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G)
- Physical Implementation of Ara, PULP's Vector Machine (1-2S)
- Manycore System on FPGA (M/S/G)
- Transforming MemPool into a CGRA (M)
- Efficient Synchronization of Manycore Systems (M/1S)
- Evaluating memory access pattern specializations in OoO, server-grade cores (M)
- Hypervisor Extension for Ariane (M)
- RISC-V base ISA for ultra-low-area cores (2-3G)
- IP-Based SoC Generation and Configuration (1-3S/B)
- SystemVerilog formatter for our LowRISC-based guidelines (2-3G)
- Coherence-Capable Write-Back L1 Data Cache for Ariane (M)
- Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
Projects In Progress
- LLVM and DaCe for Snitch (1-2S)
- Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G)
- A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
- An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
- Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
- Multi issue OoO Ariane Backend (M)
- Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
- ISA extensions in the Snitch Processor for Signal Processing (M)
- A Flexible Peripheral System for High-Performance Systems on Chip (M)