High Performance SoCs
From iis-projects
Contents
People
 |
Paul Scheffler
|
Thomas Benz
- e-mail: tbenz@iis.ee.ethz.ch
- phone: +41 44 632 05 18
- office: ETZ J85
Nils Wistoff
- e-mail: nwistoff@iis.ee.ethz.ch
- phone: +41 44 632 06 75
- office: ETZ J85
Florian Zaruba
- e-mail: zarubaf@iis.ee.ethz.ch
- phone: +41 44 632 65 56
- office: ETZ J89
Fabian Schuiki
- e-mail: fschuiki@iis.ee.ethz.ch
- phone: +41 44 632 67 89
- office: ETZ J89
Robert Balas
- e-mail: balasr@iis.ee.ethz.ch
- phone: +41 44 632 42 56
- office: ETZ J78
Projects
Available Projects
- Benchmarking RISC-V-based Accelerator Cards for Inference (multiple SA)
- Benchmarking a RISC-V-based Server on LLMs/Foundation Models (SA or MA)
- Extending our FPU with Internal High-Precision Accumulation (M)
- Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S)
- Hardware Exploration of Shared-Exponent MiniFloats (M)
- Scaleout Study on Interleaved Memory Transfers in Huge Manycore Systems with Multiple HBM Channels (M/1-3S)
- Creating an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B)
- Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S)
- Vector-based Parallel Programming Optimization of Communication Algorithm (1-2S/B)
- Routing 1000s of wires in Network-on-Chips (1-2S/M)
- Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M)
- Cycle-Accurate Event-Based Simulation of Snitch Core
- Energy Efficient AXI Interface to Serial Link Physical Layer
- Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M)
- Implementation of a Coherent Application-Class Multicore System (1-2S)
- Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G)
- Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B)
- All the flavours of FFT on MemPool (1-2S/B)
- Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Intregration
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B)
- An Efficient Compiler Backend for Snitch (1S/B)
- Towards Formal Verification of the iDMA Engine (1-3S/B)
- Serverless Benchmarks on RISC-V (M)
- Fast Simulation of Manycore Systems (1S)
- IP-Based SoC Generation and Configuration (1-3S/B)
Projects In Progress
- GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S)
- A RISC-V ISA Extension for Scalar Chaining in Snitch (M)
- Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M)
- Fault-Tolerant Floating-Point Units (M)
- Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B)
- Efficient collective communications in FlooNoC (1M)
- A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B)
- Big Data Analytics Benchmarks for Ara
- Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B)
- Runtime partitioning of L1 memory in Mempool (M)
- Vector-based Manycore HPC Cluster Exploration for 5G Communication Algorithm (1-2M)
- A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S)
- Accelerating Matrix Multiplication on a 216-core MPSoC (1M)
- Coherence-Capable Write-Back L1 Data Cache for Ariane (M)
Completed Projects
- A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
- Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S)
- Spatz grows wings: Physical Implementation of a Vector-Powered Manycore System (2S)
- Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B)
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1-3S/B)
- Investigating the Cost of Special-Case Handling in Low-Precision Floating-Point Dot Product Units (1S)
- Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M)
- Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B)
- Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B)
- Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B)
- Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)
- Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
- Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M)
- Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems
- Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S)
- Enabling Efficient Systolic Execution on MemPool (M)
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G)
- A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)
- Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B)
- Running Rust on PULP
- Optimizing the Pipeline in our Floating Point Architectures (1S)
- Design of a Prototype Chip with Interleaved Memory and Network-on-Chip
- Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
- Implementing DSP Instructions in Banshee (1S)
- Streaming Integer Extensions for Snitch (M/1-2S)
- Efficient Synchronization of Manycore Systems (M/1S)
- A Unified Compute Kernel Library for Snitch (1-2S)
- Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
- Adding Linux Support to our DMA Engine (1-2S/B)
- Hypervisor Extension for Ariane (M)
- Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
- Transforming MemPool into a CGRA (M)
- Multi issue OoO Ariane Backend (M)
- Physical Implementation of Ara, PULP's Vector Machine (1-2S)
- Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G)
- Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G)
- LLVM and DaCe for Snitch (1-2S)
- Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
- Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
- An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
- A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
- Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
- Manycore System on FPGA (M/S/G)
- A Flexible Peripheral System for High-Performance Systems on Chip (M)
- ISA extensions in the Snitch Processor for Signal Processing (M)
- A Snitch-based Compute Accelerator for HERO (M/1-2S)
- MemPool on HERO (1S)
