High Performance SoCs
From iis-projects
Contents
Contact Information
Paul Scheffler
- e-mail: paulsc@iis.ee.ethz.ch
- phone: +41 44 632 09 15
- office: ETZ J85
Thomas Benz
- e-mail: tbenz@iis.ee.ethz.ch
- phone: +41 44 632 05 18
- office: ETZ J85
Nils Wistoff
- e-mail: nwistoff@iis.ee.ethz.ch
- phone: +41 44 632 06 75
- office: ETZ J85
Projects
Available Projects
- Efficient Synchronization of Manycore Systems (M/1S)
- Evaluating memory access pattern specializations in OoO, server-grade cores (M)
- Hypervisor Extension for Ariane (M)
- RISC-V base ISA for ultra-low-area cores (2-3G)
- IP-Based SoC Generation and Configuration (1-3S/B)
- SystemVerilog formatter for our LowRISC-based guidelines (2-3G)
- Coherence-Capable Write-Back L1 Data Cache for Ariane (M)
Projects In Progress
- Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
- Manycore System on FPGA (M/S/G)
- Physical Implementation of Ara, PULP's Vector Machine (1-2S)
- Transforming MemPool into a CGRA (M)
- LLVM and DaCe for Snitch (1-2S)
- Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G)
- A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
- An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
- Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
- Multi issue OoO Ariane Backend (M)
- Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
